DETAILED ACTION
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
This Office Action is sent in response to Applicant’s Communication received on 08/09/2024 for application number 18/799,604.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 19 and 20 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. As written, claim 19 is dependent on claim 1 and simply repeats the last two limitations already recited in claim 1. Thus, claim 19 is not a further limiting dependent claim. Claim 20 is dependent on claim 19. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8, 10, 17, 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Teoh et al. (US 2019/0041936 A1).
Regarding claim 1, Teoh teaches a circuit board (Figures 1 and 2), comprising:
a platform controller hub (PCH) (Figure 2, PCH SoC 230), comprising a clock request pin (Figure 2, CLKREQ# GPIO 256 a) and a general-purpose input/output B (GPIOB) pin (Figure 2, GPIO 256 b); and
a peripheral component connector (Figure 2, attached devices 270a, 270b), comprising a first connector pin (“The CLKREQ# GPIO 256 a and 256 b can be used as an IO to the connected devices 270 a and 270 b, and can sample the state of the CLKREQ# pin [on the device side] and drive the wire state to FIA 236.” Par 0047);
a switch controlled by the GPIOB pin and coupled between a low potential and a line between the first connector pin and the clock request pin (“If “1” CLKREQ# Transmit Buffer is enabled, else if “0” CLKREQ# Transmit Buffer is Disable” par 0054 (Table 3) and “By instructing PCH FIA to deassert the CLKREQ# GPIO pin, FIA will control the GPIO pin to tristate mode, hence allow the device overtake to deassert the CLKREQ# pin when required.” Par 0055 and “The CLKREQ # GPIO pin 256 a and 256 b will be connected to ICC at PCH SoC, so that device can request for reference clock supply/gate through CLKREQ# assertion/ deassertion respectively.” Par 0048 and “PCH FIA can also drive the CLKREQ# GPIO pin to assert, to prevent the device reentering to CLKREQ# deassert power management state.” Par 0068) [the transmit buffer corresponds to the switch that either drives the signal to active low potential or enters tristate mode to disconnect the line based on the PCH GPIO pin status, corresponding to controlling the request path between the PCH and the peripheral’s pins], and configured to:
connect the line with the low potential based on a high potential of the GPIOB pin (“Presents the Active High CLKREQ transmit value. If “1” CLKREQ# Transmit Buffer is enabled” par 0054); and
disconnect the line from the low potential based on a low potential of the GPIOB pin (“else if “0” CLKREQ# Transmit Buffer is Disable” par 0054 and “By instructing PCH FIA to deassert the CLKREQ# GPIO pin, FIA will control the GPIO pin to tristate mode,” par 0055).
Claim 10 corresponds to claim 1 and is rejected accordingly. Claim 19 repeats the same limitations as recited claim 1 and is rejected accordingly.
Regarding claim 8, Teoh teaches the circuit board as claimed in claim 1, wherein the peripheral component connector is a peripheral component interconnect express (“ICC 252 can generate a reference Clock (REFCLK#) to the PCIe Devices 270 a and/or 270 b.” par 0047).
Claim 17 corresponds to claim 8 and is rejected accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 5, 11, 14, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Teoh in view of Rui et al. (US 2010/0293394 A1).
Regarding claim 2, Teoh teaches the circuit board as claimed in claim 1. However, Teoh does not explicitly teach wherein the switch comprises a gate, a drain and a source, the gate is electrically coupled to the GPIOB pin, and the drain is electrically coupled to the line, and the source is electrically coupled to the low potential.
In the analogous art, Rui teaches wherein the switch comprises a gate, a drain and a source (“the FET Q2 can be an n-channel metal oxide semiconductor (NMOS) FET” par 0010 and Figure 2), the gate is electrically coupled to the GPIOB pin (“A collector of the transistor Q1 is connected to a power supply 5V_SYS via the second resistor R2, and also connected to a gate of the FET Q2.” Par 0010), and the drain is electrically coupled to the line (“A drain of the FET Q2 is connected to the control pin GFX_VR_EN of the power supply generating module 103” par 0010), and the source is electrically coupled to the low potential (“A source of the FET Q2 is grounded.” Par 0010).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Teoh and Rui before him before the effective filing date of the claimed invention, to have modified Teoh to incorporate the teachings of Rui because both are directed at power supply control within a circuit. Incorporating a switch as taught in Rui to the teachings of Teoh would prevent electricity waste. (Rui, paragraph 4)
Claims 11 and 20 correspond to claim 2 and are rejected accordingly.
Regarding claim 5, Teoh teaches the circuit board as claimed in claim 1. However, Teoh does not explicitly teach wherein the low potential is a grounding potential.
In the analogous art, Rui teaches wherein the low potential is a grounding potential (“A source of the FET Q2 is grounded.” Par 0010 and “the ground pin B22 of the graphic card 106 is at low level, such as 0V,” par 0011) [the ground corresponds to 0V low logic level].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Teoh and Rui before him before the effective filing date of the claimed invention, to have modified Teoh to incorporate the teachings of Rui because both are directed at power supply control within a circuit. Ensuring that the low potential is a grounding potential would prevent electricity waste. (Rui, paragraph 4)
Claim 14 corresponds to claim 5 and is rejected accordingly.
Claims 3, 4, 12, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Teoh in view of Wang et al. (US 2009/0172444 A1).
Regarding claim 3, Teoh teaches the circuit board as claimed in claim 1. However, Teoh does not explicitly teach further comprising: a basic input/output system (BIOS), configured to: determine whether a graphics card connected to the peripheral component connector supports an energy-saving function; and based on the graphics card supporting the energy-saving function, turn off the switch.
In the analogous art, Wang teaches a basic input/output system (BIOS) (Figure 2, BIOS 1a), configured to:
determine whether a graphics card connected to the peripheral component connector supports an energy-saving function (“the power-saving function can be added to the BIOS of the computer system 1, 1 a. When turning on the power of the computer system 1, 1 a, the user can use a keyboard to go into the BIOS to select the power-saving function, and the user can set the chosen slot 22 a, 22 b, 22 c in the cut-off state.” Par 0019); and
based on the graphics card supporting the energy-saving function, turn off the switch (“After changing the BIOS setting and rebooting the computer system 1, 1 a, the computer system 1, 1 a will send out the controlling signal to the switch set 24 a, 24 b, 24 c of the corresponding slot 22 a, 22 b, 22 c according to the BIOS setting in order to cut off the power, the clock, and the bus signal.” Par 0019 and Figure 3).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Teoh and Wang before him before the effective filing date of the claimed invention, to have modified Teoh to incorporate the teachings of Wang to turn off the switch is the graphics card supports power saving to prevent operation errors and prevent the computing system from crashes or data processing errors. (Wang, paragraph 17)
Claim 12 corresponds to claim 3 and is rejected accordingly.
Regarding claim 4, Teoh and Wang teach the circuit board as claimed in claim 3, wherein the BIOS is further configured for:
based on the graphics card not supporting the energy-saving function, turn on the switch (“every time the computer system 1, 1 a is turned on, each slot 22 a, 22 b, 22 c will remain in the corresponding conducting or cut-off state according to the BIOS setting.” Par 0019 and Figure 3).
Claim 13 corresponds to claim 4 and is rejected accordingly.
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Teoh in view of Chou et al. (US 10,929,320 B1).
Regarding claim 6, Teoh teaches the circuit board as claimed in claim 1. However, Teoh does not explicitly teach wherein the platform controller hub further comprises a general-purpose input/output A (GPIOA) pin, the peripheral component connector further comprises a second connector pin, and the GPIOA pin is coupled to the second connector pin.
In the analogous art, Chou teaches wherein the platform controller hub further comprises a general-purpose input/output A (GPIOA) pin (“The GPIO pins for outputting a bifurcation control signal from the BMC 122 (in FIG. 1) allows for control of the bifurcation setting” col. 5, ll. 65-67), the peripheral component connector further comprises a second connector pin (“The input present line 136 provides an input present signal from the OCP 3.0 device 110 indicating presence of and information about the bifurcation capability of OCP 3.0 device 110.” Col. 5, ll. 11-14) [the device connects to the system via slot 112, corresponding to the peripheral component connector], and the GPIOA pin is coupled to the second connector pin (“The recommendation of the OCP 3.0 Specification is to user either the BMC 122 or the PCH 124 for the bifurcation control signal to the OCP device 110.” Col. 5, ll. 58-60) [PCH uses GPIO pins to transmit/receive control signals to a peripheral device via pins of the connector].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Teoh and Chou before him before the effective filing date of the claimed invention, to have modified Teoh to incorporate the teachings of Chou to include a second GPIO pin and connector pin to create a bifurcation signal between the PCH and the peripheral device and increase the utility of the device by allowing for the bifurcation control feature to be activated during the auxiliary power transition period of the power on sequence of the device. (Chou, column 4)
Claim 15 corresponds to claim 6 and is rejected accordingly.
Allowable Subject Matter
Claims 7, 9, 16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Chang (US 2006/0282656 A1) teaches a computer system that supports two interfaces controlled by an external device. If an interface is not supported by a corresponding controller of the external device, determined by a power on self-test, a controlling unit disables the appropriate controller to conserve power.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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