Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response filed 6/17/2026 has been entered. Claims 1-20 remain pending in the present application.
Terminal Disclaimer
The terminal disclaimer filed on 6/17/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US patent 11,380,042 has been reviewed and is accepted. The terminal disclaimer has been recorded.
As a result, the previous double patenting rejection is being withdrawn.
Response to Arguments
Applicant’s response filed 6/17/2026 argued that claims 18 and 19 are directed to a statutory apparatus and system under 35 U.S.C. 101 (Remarks, pages 6-8). The argument has been fully considered, and is persuasive. Therefore, the rejections of these claims under 35 U.S.C. 101 are being withdrawn.
Applicant’s arguments with respect to the rejection of claim 1 (as well as claims 18 and 20, each reciting substantially the same limitation) under 35 U.S.C. 102(a)(1) as being anticipated by Eisemann et al., “Implicit Object Space Partitioning: The No-Memory BVH” (“Eisemann” hereinafter), have also been fully considered but are not persuasive. The rejection is maintained for the reasons set forth below.
Regarding claims 1, 18 and 20, Applicant argues:
(i) that the data present in Eisemann representing the triangular primitives is not data representing nodes of a hierarchical acceleration structure (Remarks, page 10, first paragraph);
(ii) that inferring from data representing nodes of a hierarchical acceleration structure differs from inferring from data representing primitive geometry, since Eisemann infers all hierarchical acceleration structure nodes from the primitive geometry rather than from data representing nodes (Remarks, page 10, third paragraph);
(iii) that if the primitive data were properly regarded as data representing nodes, there would be no need for any inferring step in Eisemann (Remarks, page 11, first paragraph); and
(iv) that the data defining the parent bounding volume (the yellow box of Fig. 2 of Eisemann) cannot be inferred from the data defining the child bounding volumes (the blue and green boxes of Fig. 2), such that Eisemann fails to disclose “inferring, from data representing nodes of a hierarchical acceleration structure, data defining an implicitly represented node of the hierarchical acceleration structure” (Remarks, page 11, second paragraph).
In response, Eisemann expressly identifies its “nodes” with the scene triangles themselves, stating that “the nodes, i.e. the scene triangles, are sorted so that the child nodes can be directly derived from the parent node’s index” (Eisemann, p. 4, §3.1). Eisemann further defines the NMH as “a complete binary tree where each node recursively subdivides the geometry of the scene into two disjoint subsets represented by its two children plus two bounding triangles that span the node” (Eisemann, p. 7, second paragraph). Under the broadest reasonable interpretation, the sorted/reordered triangle data occupying each node’s position in this hierarchy — which Eisemann itself calls “the nodes” — constitutes “data representing nodes of a hierarchical acceleration structure” as recited in claim 1. Applicant’s argument (i) is therefore not persuasive: this is not merely primitive geometry considered generically, but the specific triangle data that Eisemann designates as representing each node of its hierarchy.
Argument (ii) is likewise not persuasive. Although each node is represented by its associated (bounding) triangles, the specific bounding-volume data that geometrically defines the node — its axis-aligned bounding box, or “slab” — is not separately stored anywhere in Eisemann; it exists only implicitly and must be computed. Eisemann discloses that “during traversal the AABB is reconstructed from these bounding triangles only” (Eisemann, pp. 4–5, §3.1), and the traversal algorithm computes this bounding-volume data directly from the two triangles occupying the node’s array position: “minSlab = min(tris[index], tris[index+1], axis)” and “maxSlab = max(tris[index], tris[index+1], axis)” (Eisemann, p. 9, Algorithm 2). This is “inferring, from data representing nodes ... data defining an implicitly represented node,” exactly as recited in claim 1: the source data (the triangles representing the node) is used to derive data (the AABB/slab bounds) that is not itself explicitly present anywhere in the structure. Claim 1 does not require that the recited “data representing nodes” take the form of previously computed bounding-volume coordinates from a classic BVH; it requires only that the source data represent the nodes of the hierarchical acceleration structure, which Eisemann’s own terminology confirms the sorted triangle data does.
Regarding argument (iii), there is no inconsistency between the triangle data representing a node and an inferring step remaining necessary. The triangles establish which geometry belongs to a given node (via the sorting/reordering described at p. 4, §3.1, and pp. 5–9, §3.2–3.3), but the node’s specific bounding-volume data — the data actually needed to test a ray against the node, i.e., the “data defining an implicitly represented node” — is never stored and must still be computed at traversal time, as shown by the minSlab/maxSlab computation of Algorithm 2 (Eisemann, p. 9). Far from rendering the inferring step unnecessary, Eisemann’s entire premise is that this computation replaces what a classic BVH would otherwise store explicitly (Eisemann, p. 1, Introduction: each bounding plane of a BVH node corresponds to a vertex in the scene geometry, such that “if one knows ... which scene point is responsible for spanning the current node, the acceleration data structure itself becomes redundant”).
Regarding argument (iv), claim 1 does not require that a parent node’s data be inferable from a child node’s data, nor does it preclude a scheme in which the bounding-volume data for every node in the hierarchy — including a node corresponding to the yellow box of Fig. 2 — is independently inferred from that node’s own associated triangle data, rather than from another node’s already-computed bounds. Eisemann’s Definition (p. 7, §3.3) confirms that each node’s bounding triangles “represent conservative bounds on the geometric extent” of that node specifically, and the traversal algorithm (p. 9, Algorithm 2) computes each node’s bounds independently from its own two bounding triangles at every level of the tree, whether that node is a parent (e.g., the yellow box) or a child (e.g., the blue or green boxes). Applicant’s observation that the yellow box cannot be inferred from the blue and green boxes is accordingly consistent with, rather than contrary to, Eisemann’s disclosure, and does not distinguish Eisemann from claim 1.
For at least these reasons, Eisemann discloses each and every limitation of claim 1 (and similarly, claims 18 and 20), and the rejections of these claims under 35 U.S.C. 102(a)(1) are maintained.
Claim Interpretation
The following is a quotation of 35 U.S.C. §112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. §112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. §112(f) or pre-AIA 35 U.S.C. §112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a node processing module”, “node processing logic”, “one or more processing blocks”, “a processing module”, and “processing logic” in claims 18 and 19.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. §112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
A review of the specification shows that the following appears to be the corresponding structure described in the specification for the 35 U.S.C. §112(f) or pre-AIA 35 U.S.C. §112, sixth paragraph limitation: the integrated circuit (IC) disclosed in the last paragraph on page 47 the specification, which is a specialized IC when it is configured to run the algorithm shown in Fig. 6.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. §112(f) or pre-AIA 35 U.S.C. §112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. §112(f) or pre-AIA 35 U.S.C. §112, sixth paragraph; or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. §112(f) or pre-AIA 35 U.S.C. §112, sixth paragraph.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 12, 15 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eisemann et al. (“Implicit Object Space Partitioning: The No-Memory BVH”, 2011).
Regarding claim 1, Eisemann discloses a computer-implemented method for use in a ray tracing system, the method comprising:
inferring, from data representing nodes of a hierarchical acceleration structure, data defining an implicitly represented node of the hierarchical acceleration structure (See the Abstract and section 3.1 Overview, 2nd paragraph: “Our No-Memory Hierarchy (NMH) works in very much the same way, only that the bounds of the BVH nodes are derived directly from the primitive information itself. Our main observation here is that each side of the AABB is defined by at least one triangle vertex. Accordingly it is sufficient to find the six vertices and their according triangles that span the AABB to recreate the bounds. These bounding triangles can be computed in advance. An example is given in Figure 2”. In particular, since the bounds of a BVH node can be inferred from a number of triangle vertices, the BVH node could be viewed as an implicitly-represented node. In the example illustrated in Fig. 2, triangles 0-11 constitute data representing nodes of a hierarchical acceleration structure, and triangles 4-7 constitute data defining the blue-colored implicitly-represented node); and
using the inferred data to process the implicitly represented node in the ray tracing system (Section 3.1 Overview, 2nd paragraph: “During traversal the AABB is reconstructed from these bounding triangles only. If the ray intersects with the box these triangles are tested before the traversal continues with the child nodes”).
Regarding claim 2, Eisemann discloses the method of claim 1, wherein the using the inferred data to process the implicitly represented node in the ray tracing system comprises testing a ray for intersection with a region represented by the implicitly represented node of the hierarchical acceleration structure (Section 3.1 Overview, 2nd paragraph: “During traversal the AABB is reconstructed from these bounding triangles only. If the ray intersects with the box these triangles are tested before the traversal continues with the child nodes”).
Regarding claim 3, Eisemann discloses the method of claim 1, further comprising receiving the data representing nodes of the hierarchical acceleration structure (Section 3.1 Overview, 2nd paragraph: “These bounding triangles can be computed in advance... Therefore, a node in our NMH is essentially only a small set of triangles contiguously mapped in memory”).
Regarding claim 4, Eisemann discloses the method of claim 1, wherein data defining a region represented by the implicitly represented node is not explicitly included as part of said data representing nodes of the hierarchical acceleration structure (In Eisemann, the bounds of a BVH node is not explicitly included as part of the data representing nodes of a hierarchical acceleration structure. Rather, the bounds are inferred from triangle vertices).
Regarding claim 5, Eisemann discloses the method of claim 1, wherein the data defining the implicitly represented node comprises data defining a region represented by the implicitly represented node (See Fig. 3 of Eisemann and the associated caption. The bounds of a BVH node defines a region, and these bounds can be derived from triangle vertices).
Regarding claim 6, Eisemann discloses the method of claim 2, wherein a result of testing the ray for intersection with the region represented by the implicitly represented node is used for determining a rendered value (Section 3 Implicit Object Space Partitioning, 1st paragraph: "We propose a simple ray tracing algorithm which offers interactive rendering times for both static and dynamic scenes". It is well known in the art that the color value at the intersection of a ray with a surface is used for determining a rendered value).
Regarding claim 7, Eisemann discloses the method of claim 1, further comprising grouping rays into packets to be tested for intersection with regions represented by nodes of the hierarchical acceleration structure (Abstract: “The implicit acceleration data structure must be constructed only once and can be reused for arbitrary numbers of rays or ray batches without the need to rebuild the hierarchy”) for which data is received in a data block (Section 3.1 Overview, 2nd paragraph: “a node in our NMH is essentially only a small set of triangles contiguously mapped in memory”).
Regarding claim 8, Eisemann discloses the method of claim 5, wherein the data defining the region represented by the implicitly represented node is inferred using data defining regions represented by at least some of the nodes of the hierarchical acceleration structure (Section 3.1 Overview, 2nd paragraph: “The nodes, i.e. the scene triangles, are sorted so that the child nodes can be directly derived from the parent nodes index”. In particular, the bounds of an implicitly-represented child node can be inferred from its parent node index).
Regarding claim 12, Eisemann discloses the method of claim 1, wherein said data representing nodes of the hierarchical acceleration structure comprises one or more data blocks (Fig. 3 shows 6 data blocks in the memory each of which represents a BVH node), wherein a data block comprises data representing a sub-tree within the hierarchical acceleration structure (In Fig. 3, the data block comprising triangles 2 and 3 represents a left sub-tree), wherein the sub-tree comprises one or more nodes at a plurality of levels within the hierarchical acceleration structure (The aforementioned left sub-tree comprises three nodes at two different levels within the hierarchical acceleration structure), wherein the data block comprises: (i) data defining regions represented by the nodes at the lowest level of the sub-tree (In Fig. 3, data blocks 6-7 and 8-9 comprise data defining regions represented by the nodes at the lowest level of the left sub-tree), and (ii) data indicating how the nodes of the sub-tree are linked (In Algorithm 1, the left and right children of a node can be accessed by calling the functions indexForLeftChild() and indexForRightChild(), respectively. This suggests that there is data (e.g. the indices) indicating how the child nodes are linked to their parent node).
Regarding claim 15, Eisemann discloses the method of claim 12, wherein the data block comprises data defining regions which are represented by nodes having a shared ancestor in the hierarchical acceleration structure (In Fig. 3, the data block comprising triangles 2 and 3 comprises data defining regions which are represented by nodes 6-7and 8-9 having a shared ancestor (node 2-3) in the hierarchical acceleration structure), the data block further comprising an indication of a common origin region (In Algorithm 1, the functions indexForLeftChild() and indexForRightChild() both have an argument index, which indicates the index of the current (parent) node. This index value could be viewed as an indication of a common origin region (the parent node region)) and wherein the data in the data block defining the regions which are represented by nodes having a shared ancestor in the hierarchical acceleration structure comprises, for each of the nodes having the shared ancestor, one or more offsets from the common origin region, wherein the common origin region represents the region represented by the shared ancestor (Section 3.2 Representation, 2nd paragraph: “Index zero is the first triangle in the root node. For any other node whose first triangle index is i its children, i.e. the first triangle in the respective nodes, are indexed with ik +2m where k is the branching factor”).
Claim 18 could be rejected using the same rationale set forth in the rejection of claim 1 because Eisemann also discloses the claimed “node processing logic” and “one or more processing blocks” (See Algorithm 1. The code used to compute an AABB from six triangles corresponds to the claimed “node processing logic”, and the code used to test if the AABB is hit corresponds to the claimed “one or more processing blocks”). The algorithm, when run on a specialized IC, makes the IC a node processing module.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-11 and 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eisemann, in view of Hazel (Pub. No. 2019/0035147).
Regarding claim 9, Eisemann discloses the method of claim 8
Eisemann, however, does not disclose the above lined-through limitation. In other words, Eisemann does not disclose that the bounds of an implicitly-represented node can be inferred from those of its children.
In the same field of computer graphics, Hazel teaches the above limitation (See par. 136).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Eisemann by inferring the bounds of a parent node from those of its children, as taught by Hazel. The motivation would have been to be able to infer the bounds of an implicitly-represented node from either an upper or lower level.
Regarding claim 10, Eisemann in view of Hazel teaches the method of claim 9, wherein either: (i) the descendants of the implicitly represented node at the particular level in the hierarchical acceleration structure are the children of the implicitly represented node in the hierarchical acceleration structure, or (ii) the descendants of the implicitly represented node at the particular level in the hierarchical acceleration structure are the grandchildren of the implicitly represented node in the hierarchical acceleration structure (As disclosed by Hazel in par. 136, the bounds of an implicitly-represented node can be derived from those of its children).
Regarding claim 11, Eisemann in view of Hazel teaches the method of claim 9, wherein the regions represented by the nodes of the hierarchical acceleration structure are axis-aligned bounding boxes in the scene (The term “AABB” used throughout the literature of Eisemann stands for “axis-aligned bounding boxes”, as is well known in the art), and wherein the data defining the region represented by the implicitly represented node is inferred by determining, in each dimension of the scene, a minimum and a maximum component of the components defining the axis-aligned bounding boxes represented by the descendants of the implicitly represented node at the particular level in the hierarchical acceleration structure (Hazel, par. 136: “a bounding volume for the parent node that entirely encompasses all the bounding volumes of the child nodes could be determined (and in an embodiment this is done). In this case, the bounding volume for the parent node could be, and is in an embodiment, generating by taking the minimum and maximum vertex position values along each axis across all of the parent node's child nodes”).
Regarding claim 13, Eisemann discloses the method of claim 12, wherein at least one node of the sub-tree which is at a level above the lowest level of the sub-tree is an implicitly represented node which is implicitly represented by the data in the data block,
In the same field of computer graphics, Hazel teaches the bounds of a node can be derived from those of its child nodes (See par. 136).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Eisemann such that the bounds of node 2-3 could be derived from the bounds of its child nodes, 6-7 and 8-9, as taught by Hazel. The motivation would have been to be able to infer the bounds of an implicitly-represented node from either an upper or lower level.
Regarding claim 14, Eisemann in view of Hazel teaches the method of claim 13, wherein the implicitly represented node is the parent node in the sub-tree for said at least some of the nodes at the lowest level of the sub-tree (In Fig. 3 of Eisemann, node 2-3 is the parent node in the left sub-tree for said at least some of the nodes at the lowest level of the sub-tree (i.e. nodes 6-7 and 8-9)).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eisemann, in view of Asukai et al. (Pub. No. US 2014/0270574).
Regarding claim 16, Eisemann discloses the method of claim 12, wherein said data representing at least part of a hierarchical acceleration structure is received from a memory
Eisemann, however, does not disclose the above lined-through limitation.
In the same field of image rendering, Asukai teaches that when reading and writing image data on a memory on a pixel-block by pixel-block basis, the time required for data transfer can be reduced if the size of each pixel block is adjusted so as to match the burst length (Par. 6).
In light of the above teaching of Asukai, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Ozdas by configuring the size of a data block such that it would match the minimum burst size of the memory. The motivation would have been to reduce the time required for data transfer.
Claim(s) 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eisemann, in view of Lee et al. (Pub. No. US 2017/0061674).
Regarding claim 17, Eisemann discloses a method of rendering an image of a scene in a ray tracing system comprising:
generating a hierarchical acceleration structure (The No-Memory Hierarchy (NMH) taught by Eisemann is a hierarchical acceleration structure because it is based on the bounding volume hierarchy (BVH), which is a hierarchical acceleration structure);
performing intersection testing as set forth in claim 2 using at least part of the generated hierarchical acceleration structure (See the rejection of claim 2)
Eisemann does not disclose the above lined-through limitation.
In the same field of ray tracing, Lee teaches executing one or more shader programs to process results of intersection testing to determine rendered values representing an image of a scene (See the abstract and pars. 14-16).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to include one or more shader programs in Eisemann such that when executed, the one or more shader programs would process results of the intersection testing to determine rendered values representing the image of the scene, as taught by Lee. The motivation would have been because shader programs in ray tracing offer unmatched realism, flexibility, and performance. They bridge the gap between geometric ray casting and the complex lighting and material calculations needed for photorealistic images, while modern optimizations ensure they remain efficient even in demanding real-time scenarios.
Claim 19 recites similar limitations as claim 17, but is directed to a system. Since the claimed “processing module”, “node processing module”, and “processing logic” could be collectively viewed as a specialized IC when it executes the algorithm 1 of Eisemann, claim 19 could be rejected under the same rationale set forth in the rejection of claim 17.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eisemann, in view of Howson et al. (Pub. No. US 2017/0309059).
Claim 20 recites similar limitations as claim 18, but is directed to a computer readable storage medium having stored thereon an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture a node processing module as claimed in claim 18. Although Eisemann does not disclose such a storage medium, Howson does (See par. 104). Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to incorporate the teaching of Howson into Eisemann in order to commercialize the technique.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PHONG X NGUYEN/ Primary Patent Examiner, Art Unit 2617
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