DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rhoades (US 2003/0226000).
In regards to claim 1, Rhoades discloses of a pipeline circuit, comprising: a gating circuit (40), configured to receive an input signal at an input end, and selectively output the input signal as an output signal at an output end, wherein in a first mode, the gating circuit (40) receives the input signal that has been gated to output as the output signal; and wherein in a second mode, the gating circuit (40) receives the input signal to output as the output signal (see Fig 3 and Paragraphs 0030-0034).
In regards to claim 2, Rhoades discloses of the pipeline circuit according to claim 1, comprising: a pre-stage gating circuit (34), wherein in the first mode, the input signal is gated by the pre-stage gating circuit (34) and then input to the gating circuit (40), and in the second mode, the input signal bypasses the pre-stage gating circuit (34) and is input to the gating circuit (40, see Fig 3 and Paragraphs 0030-0034).
In regards to claim 3, Rhoades discloses of the pipeline circuit according to claim 2, comprising: a select circuit (36), coupled between the pre-stage gating circuit (34) and the gating circuit (40), wherein the select circuit (36) has a first input end coupled to an input end of the pre-stage gating circuit (34), a second input end coupled to an output end of the pre-stage gating circuit (34), and an output end coupled to the input end of the gating circuit (40, see Fig 3 and Paragraphs 0030-0034).
In regards to claim 4, Rhoades disclose of the pipeline circuit according to claim 3, wherein the select circuit (36) is configured to couple the second input end of the select circuit (36) to the output end of the select circuit (36) in the first mode, and couple the first input end of the select circuit (36) to the output end of the select circuit (36) in the second mode (see Fig 3 and Paragraphs 0030-0034).
In regards to claim 5, Rhoades discloses of the pipeline circuit according to claim 4, wherein in the first mode, both the pre-stage gating circuit (34) and the gating circuit (40) receive a first clock signal (CLK under un-collapsed conditions) at respective clock ends, wherein in the second mode, the clock end of the pre-stage gating circuit (34) is blocked (via 42), and the clock end of the gating circuit (40) receives a second clock signal (CLK under collapsed conditions, see Figs 2-3 and Paragraphs 0013, 0018, 0028-0034).
In regards to claim 6, Rhoades discloses of the pipeline circuit according to claim 5, wherein a frequency of the first clock (CLK under un-collapsed conditions) signal is higher than a frequency of the second clock signal (CLK under collapsed conditions, see Figs 2-3 and Paragraphs 0013, 0018, 0028-0029, frequency scaled down).
In regards to claim 7, Rhoades discloses of a pipeline operating method, comprising: receiving an input signal by a gating circuit (40), and selectively outputting the input signal as an output signal, wherein in a first mode, the input signal that has been gated is received by the gating circuit (40) to output as the output signal; and wherein in a second mode, the input signal is received by the gating circuit (40) to output as the output signal (see Fig 3 and Paragraphs 0030-0034).
In regards to claim 8, Rhoades discloses of the pipeline operating method according to claim 7, wherein in the first mode, the input signal is gated by a pre-stage gating circuit (34) and then input to the gating circuit (40); and in the second mode, the input signal bypasses the pre-stage gating circuit (34) and is input to the gating circuit (40, see Fig 3 and Paragraphs 0030-0034).
In regards to claim 9, Rhoades discloses of the pipeline operating method according to claim 8, comprising coupling an output end of the pre-stage gating circuit (34) to an input end of the gating circuit (40) in the first mode by a select circuit (36), and coupling an input end of the pre-stage gating circuit (34) to the input end of the gating circuit (40) in the second mode by the select circuit (36, see Fig 3 and Paragraphs 0030-0034).
In regards to claim 10, Rhoades discloses of the pipeline operating method according to claim 9, comprising: in the first mode, providing a first clock signal (CLK under un-collapsed conditions) to clock ends of the pre-stage gating circuit (34) and the gating circuit (40), and in the second mode, blocking (via 42) the clock end provided to the pre-stage gating circuit (34), and providing a second clock signal (CLK under collapsed conditions) to the clock end of the gating circuit (40, see Figs 2-3 and Paragraphs 0013, 0018, 0028-0034).
In regards to claim 11, Rhoades discloses of the pipeline operating method according to claim 10, wherein a frequency of the first clock signal (CLK under un-collapsed conditions) is higher than a frequency of the second clock signal (CLK under collapsed conditions, see Figs 2-3 and Paragraphs 0013, 0018, 0028-0029, frequency scaled down).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason M Crawford whose telephone number is (571)272-6004. The examiner can normally be reached Mon-Fri 6:00am-3:00pm.
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2844