DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 7-8, 10-11 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Khlat (USPAPN 2022/0123744).
With respect to claim 1, Khlat discloses, in Fig. 2, an amplification system for performing symbol power tracking (SPT) (Fig. 2 providing per-symbol power tracking, see para 0005), the amplification system comprising:
a first voltage output circuit (e.g., 48) configured to output a first power supply voltage (Vsup, see also Fig. 3, note VSUP is the bypasses 34 and is supplied as VOUT-N);
a second voltage output circuit (34) configured to output a second power supply voltage (an additional one of VOUT-1 to VOUT-2, e.g., VOUT-1, note 34 generates the other voltages that are not the VOUT-N value, see Fig. 3);
a first amplification circuit (52B);
a second amplification circuit (52A); and
a first switch configured (36B) to, in a first mode (according to the control of 46B), selectively perform switching between a connection of the first voltage output circuit and the first amplification circuit and a connection of the second voltage output circuit and the first amplification circuit (“mode” where two symbols cause 46B to control 36B such that 38 generates VCCB as VOUT-N and then subsequently VCCB as VOUT-1. Note, 36A and 36B may select any desired voltage of VOUT-1 to VOUT-N according to 46A and 46B as required on the pre-symbol basis, see paragraphs 0026, 0028 and 0029) and, in a second mode, connect the first voltage output circuit and the first amplification circuit and connect the second voltage output circuit and the second amplification circuit (mode where 46A and 46B control 36A and 36B such that VOUT-N is provided to 52B while VOUT-1 is provided to 52A).
With respect to claim 3, the amplification system according to claim 1, wherein the first mode is an SPT mode (the first mode may be considered an SPT mode, since the change in symbol causes the change in the level of the VCCB voltage level), and the second mode is an average power tracking (APT) mode (the second mode may be considered an APT mode, since each voltage level for each symbol is selected according to the APT/average power for that symbol, see paragraph 0004).
With respect to claim 7, the amplification system according to claim 1, wherein: the first amplification circuit is configured to amplify a radio frequency signal of an ultra-high band group (i.e., band of 5 GHZ, see paragraph 0039), and the second amplification circuit is configured to amplify a radio frequency signal of a low band group and a radio frequency signal of a middle-high band group (i.e., band of 2.4 GHz, see paragraph 0038. No explicitly claimed value is given for “ultra-high band group”, “low band group” and “middle-high band group”. As can be seen 2.4 GHz is lower than 5 GHZ. Thus, 5 GHz may be interpreted as the “ultra-high band group” and the lower frequency 2.4 GHz may be interpreted as one of the “low” and/or “middle-high” band groups).
With respect to claim 8, the amplification system according to claim 1, further comprising:
a second switch (36A, or 36A with 36B) configured to, in a fourth mode, selectively perform switching between a connection of the first voltage output circuit and the second amplification circuit and a connection of the second voltage output circuit and the second amplification circuit (“mode” where two consecutive symbols require 36A to select between VOUT-N and VOUT-1) and, in the second mode, connect the first voltage output circuit and the first amplification circuit and connect the second voltage output circuit and the second amplification circuit (during the above second mode the circuit is operative as claimed due to the voltages of VCCB and VCCA being at VOUT-N and VOUT-1).
With respect to claim 10, the amplification system according to claim 8, wherein the fourth mode is an SPT mode (the fourth mode is an SPT mode, since VCCA is changed on a pre-symbol basis).
With respect to claim 11, an amplification module for performing SPT (Fig. 2), the amplification module comprising:
a first power supply voltage terminal (VSUP, i.e., VOUT-N, terminal see Fig. 3) to which a first power supply voltage is applied (VOUT-N) and a second power supply voltage terminal (VOUT-1 terminal) to which a second power supply voltage is applied (VOUT-1);
a first amplification circuit (52B);
a second amplification circuit (52A) connected to the second power supply voltage terminal (when 38A selects VOUT-N); and
a first switch (36B) that includes a first common terminal (38B), a first selection terminal (terminal connected to VOUT-N), and a second selection terminal (terminal connected to VOUT-1), wherein the first common terminal is connected to the first amplification circuit (at the VCCB node), the first selection terminal is connected to the first power supply voltage terminal (VOUT-N is connected to the first terminal), and the second selection terminal is connected to the second power supply voltage terminal (VOUT-1 is connected to the second terminal).
With respect to claim 14, the amplification module according to claim 11, further comprising:
a second switch (36A) that includes a second common terminal (38A), a third selection terminal (terminal connected to VOUT-1), and a fourth selection terminal (terminal connected to VOUT-N), wherein the second common terminal is connected to the second amplification circuit (at VCCA), the third selection terminal is connected to the second power supply voltage terminal (the third selection terminal is connected to VOUT-1), and the fourth selection terminal is connected to the first power supply voltage terminal (the fourth selection terminal is connected to VOUT-N).
Claim(s) 1-2, 4, 11, 14 and 16-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (USPAPN 2021/0083635).
With respect to claim 1, Kim et al. discloses, in Figs. 3-6, an amplification system for performing symbol power tracking (SPT) (one of Figs. 3. Details of operation disclosed in Figs. 4-5C.), the amplification system comprising:
a first voltage output circuit (111, see also Fig. 6) configured to output a first power supply voltage (Vs1);
a second voltage output circuit (112, see also Fig. 6) configured to output a second power supply voltage (Vs2);
a first amplification circuit (PAM2);
a second amplification circuit (PAM3); and
a first switch configured (120 of Fig. 3) to, in a first mode (Mode3 see Fig. 4 and 5C), selectively perform switching between a connection of the first voltage output circuit and the first amplification circuit and a connection of the second voltage output circuit and the first amplification circuit (when transitioned from Mode2, see Figs. 4 and 5B, and during Mode3, see Figs. 4 and 5C the connection between SW1 and SW2, i.e., the connection between Vs1 and Vs2 and the first amplification circuit PAM2 is selective switched between Vs1 to Vs2 by opening SW1 and closing SW2, see Fig. 5c) and, in a second mode (Mode2, see Figs. 4 and 5B), connect the first voltage output circuit and the first amplification circuit (SW1 is closed and Vs1 is connected to PAM2) and connect the second voltage output circuit and the second amplification circuit (112 is connected to PAM3 in Mode2).
With respect to claim 2, the amplification system according to claim 1, wherein: when the first amplification circuit performs an amplification operation and the second amplification circuit does not perform an amplification operation, the first mode is performed (during the first mode of Mode3 PAM2 is on and PAM3 is off, see Fig. 5C), and when the first amplification circuit and the second amplification circuit simultaneously perform an amplification operation, the second mode is performed (during the second mode of Mode2 PAM2 is on and PAM3 is on).
With respect to claim 4, the amplification system according to claim 1, wherein the first voltage output circuit includes a linear amplifier circuit that generates a voltage based on an envelope signal (e.g. linear regulator of 110_1 to provided envelope tracking, see paragraph 0072), and a DC/DC converter that generates a DC voltage (i.e., switching regulator that is summed with the linear regulator to generate Vs, see paragraph 0072).
With respect to claim 11, Kim et al. discloses, in Fig. 8, an amplification module for performing SPT (Fig. 8), the amplification module comprising:
a first power supply voltage terminal to which a first power supply voltage is applied (Vs1 terminal and voltage) and a second power supply voltage terminal to which a second power supply voltage is applied (Vs2 terminal and voltage);
a first amplification circuit (PAM2);
a second amplification circuit connected to the second power supply voltage terminal (PAM3); and
a first switch (SW1 with SW2) that includes a first common terminal (terminal between SW1 and SW2), a first selection terminal (Vs1 terminal of SW1), and a second selection terminal (Vs2 terminal of SW2), wherein the first common terminal is connected to the first amplification circuit (node between SW1 and SW2 connected to PAM2), the first selection terminal is connected to the first power supply voltage terminal (Vs1), and the second selection terminal is connected to the second power supply voltage terminal (Vs2).
With respect to claim 14, the amplification module according to claim 11, further comprising:
a second switch (SW3 with SW4) that includes a second common terminal (node between SW3 and SW4), a third selection terminal (Vs2 terminal of SW4), and a fourth selection terminal (Vs1 terminal of SW3), wherein the second common terminal is connected to the second amplification circuit (node between SW3 and SW4 connected to PAM3), the third selection terminal is connected to the second power supply voltage terminal (Vs2), and the fourth selection terminal is connected to the first power supply voltage terminal (Vs1).
With respect to claim 16, Kim et al. discloses, in Figs. 3-5C, a method of driving an amplification system configured to perform SPT,(method of operating the circuit of Fig. 3 operational details disclosed in Figs. 4-5C) the method comprising:
supplying a power supply voltage (voltage supplied to the node between SW1 and SW2, i.e., selected Vs1 and Vs2) to the amplification system (PAM2) in a mode including a first mode (Mode3, see Figs. 4 and 5C) and a second mode (Mode2 see Figs. 4 and 5B),
wherein, in the first mode, a first power supply voltage and a second power supply voltage are selectively switched to initiate a first amplification circuit to perform an amplification operation and configure a second amplification circuit not to perform an amplification operation (in the first mode of Mode3 SW1 and SW2 selectively changes from supply Vs1 to supply Vs2 when PAM2 is operative and PAM3 is off, see Fig. 5C) , and
wherein, in the second mode, the first amplification circuit and the second amplification circuit are simultaneously configured to perform an amplification operation (in Mode2, both PAM2 and PAM3 are on/operative, see Fig. 5B).
Wither respect to claim 17, the method of driving an amplification system according to claim 16, wherein the first mode is an SPT mode (selective according to the bands/symbols amplified by PAM2 and PAM1), and the second mode is an APT mode (APT as controlled by 111 and/or 112, see 110_2 of Fig. 6).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (USPAPN 2021/0083635).
Kim et al. fails to explicitly disclose whether or not the devices of Fig. 3 are integrated into a single chip, multiple chips or constructed from discrete components. Thus, Kim et al. fails to disclose the “amplification module according to claim 11, further comprising:
a module laminate at which the first power supply voltage terminal, the second power supply voltage terminal, the first amplification circuit, the second amplification circuit, and the first switch are disposed,
wherein the first power supply voltage terminal and the second power supply voltage terminal are external connection terminals of the amplification module.”
However, it is old and well-known connected multiple devices within the same integrated circuit chip/die/substrate (i.e., module laminate) for the purposes of decreasing the overall circuit space required to constructed the combined multiple devices/circuit. Furthermore, it is known that constructing other devices external to the integrated circuit for the purpose of making it easier to replace the external devices when the devices of the external device are damaged and/or it is desired to repair, change and/or upgrade the external devices.
It would have been obvious to construct the circuit of Fig. 3 (lest 111 and 112) on the same integrated circuit chip/die/substrate, since it has been held that forming one piece of an article which has formerly been formed in two pieces and put together involves only routine skill in the art, Howard v. Detroit Stove Works, 150 U.S. 164 (1893). One would have been motivated to do so to reduced the area required to construct the circuitry. Furthermore, it would have been obvious to construct the circuit of Fig. 3 such that 111, 112, Vs1 and/or Vs2 are external to the other circuitry of Fig. 3, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art, Nerwin v. Erlichman, 168 USPQ 177, 179. One would have been motivated to do so to for the purpose of making it easier to replace the external devices when the devices of the external device are damaged and/or it is desired to repair, change and/or upgrade the external devices
Allowable Subject Matter
Claims 9, 13, 15 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
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