DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Email Communication
Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 & 8-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakano et al. (US 2021/0183581).
In regards to claim 1, Nakano ‘581 discloses
A multilayer ceramic capacitor, comprising:
a multilayer body (12 – fig. 1; [0028]) including dielectric layers (16 – fig. 1; [0033]) and internal electrode layers (18a & 18b – fig. 1; [0033]) alternately laminated therein, the multilayer body including two main surfaces (12a & 12b – fig. 1; [0029]) opposed to each other in a lamination direction, two end surfaces (12c & 12d – fig. 1; [0029]) opposed to each other in a length direction orthogonal or substantially orthogonal to the lamination direction, and two lateral surfaces (12e & 12f – fig. 1; [0029]) opposed to each other in a width direction orthogonal or substantially orthogonal to both the lamination direction and the length direction; and
external electrodes (14 & 15 – fig. 1; [0028]) respectively provided on the two end surfaces of the multilayer body; wherein
each of the external electrodes includes a base electrode layer (28 – fig. 2; [0051]), a first plated layer (31 – fig. 2; [0055]) on top of the base electrode layer, a second plated layer (32-33 – fig. 2; [0055]) on top of the first plated layer, and an adhesive force mitigation layer (26 – fig. 2; [0048]) between the first plated layer and the second plated layer while allowing the second plated layer to be in contact with the first plated layer (electrical contact is present).
In regards to claim 2, Nakano ‘581 discloses
The multilayer ceramic capacitor according to claim 1, wherein the second plated layer includes an inner second plated layer (32 – fig. 2; [0055]) and an outer second plated layer (33 – fig. 2; [0055]) on top of the inner second plated layer.
In regards to claim 3, Nakano ‘581 discloses
The multilayer ceramic capacitor according to claim 2, wherein the first plated layer is a Cu plated layer;
the inner second plated layer is a Ni plated layer; and
the outer second plated layer is a Sn plated layer ([0055]).
In regards to claim 4, Nakano ‘581 discloses
The multilayer ceramic capacitor according to claim 1, wherein the adhesive force mitigation layer includes an organosilicon compound ([0078-0097]).
In regards to claim 5, Nakano ‘581 discloses
The multilayer ceramic capacitor according to claim 4, wherein the organosilicon compound is a multifunctional alkoxysilane ([0078-0097]).
In regards to claim 8, Nakano ‘581 discloses
The multilayer ceramic capacitor according to claim 1, wherein the dielectric layers include a ceramic material ([0035]).
In regards to claim 9, Nakano ‘581 discloses
The multilayer ceramic capacitor according to claim 8, wherein the ceramic material includes:
BaTiO3 as a main component; and
at least one subcomponent selected from a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound ([0035]).
In regards to claim 10, Nakano ‘581 discloses
The multilayer ceramic capacitor according to claim 1, wherein the multilayer body further includes an outer layer portion (16a – fig. 2; [0034]); and
the dielectric layers and the outer layer portion include a same ceramic material ([0034-0035]).
Claim(s) 1, 4-5, 7-8, & 10-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2021/0082622).
In regards to claim 1, Kim ‘622 discloses
A multilayer ceramic capacitor, comprising:
a multilayer body (110 – fig. 2; [0033]) including dielectric layers (111 – fig. 2; [0033]) and internal electrode layers (121 & 122 – fig. 2; [0033]) alternately laminated therein, the multilayer body including two main surfaces (1 & 2 – fig. 1; [0033]) opposed to each other in a lamination direction, two end surfaces (3 & 4 – fig. 1; [0033]) opposed to each other in a length direction orthogonal or substantially orthogonal to the lamination direction, and two lateral surfaces (5 & 6 – fig. 1; [0033]) opposed to each other in a width direction orthogonal or substantially orthogonal to both the lamination direction and the length direction; and
external electrodes (131 & 132 – fig. 1; [0033]) respectively provided on the two end surfaces of the multilayer body; wherein
each of the external electrodes includes a base electrode layer (131a/131b & 132a/132b – fig. 2; [0033]), a first plated layer (131c & 132c – fig. 2; [0033]) on top of the base electrode layer, a second plated layer (131d & 132d – fig. 2; [0033]) on top of the first plated layer, and an adhesive force mitigation layer (141-143 – fig. 2; [0033] or 141’, 142’, & 143 – fig. 6; [0123] or 141”, 142”, & 143 – fig. 8; [0124]) between the first plated layer and the second plated layer while allowing the second plated layer to be in contact with the first plated layer.
In regards to claim 4, Kim ‘622 discloses
The multilayer ceramic capacitor according to claim 1, wherein the adhesive force mitigation layer includes an organosilicon compound ([0095]).
In regards to claim 5, Kim ‘622 discloses
The multilayer ceramic capacitor according to claim 4, wherein the organosilicon compound is a multifunctional alkoxysilane ([0095]).
In regards to claim 7, Kim ‘622 discloses
The multilayer ceramic capacitor according to claim 1, wherein the adhesive force mitigation layer between the first plated layer and the second plated layer is provided in areas located over outer areas of the main surfaces and in areas located over outer areas of the lateral surfaces, and is not provided in areas located over outer areas of the corresponding end surface (fig. 2).
In regards to claim 8, Kim ‘622 discloses
The multilayer ceramic capacitor according to claim 1, wherein the dielectric layers include a ceramic material ([0038]).
In regards to claim 10, Kim ‘622 discloses
The multilayer ceramic capacitor according to claim 1, wherein the multilayer body further includes an outer layer portion (112-113 – fig. 2; [0043]); and
the dielectric layers and the outer layer portion include a same ceramic material ([0043]).
In regards to claim 11, Kim ‘622 discloses
The multilayer ceramic capacitor according to claim 1, wherein the adhesive force mitigation layer has a porous structure (fig. 6 & 8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘622 in view of Hamamori et al. (US 2018/0082787).
In regards to claim 6,
Kim ‘622 fails to disclose wherein the first plated layer has a surface roughness of about 0.10 μm or more and about 0.27 μm or less.
Hamamori ‘787 discloses wherein the surface roughness the external electrode layer adjacent to the adhesive force mitigation layer is a result effective variable, particularly for controlling the surface roughness of adhesive force mitigation layer which will ensure improved crack prevention by allowing layer peeling which prevents the propagation of stress from warpage ([0010], [0019], & [0100]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Kim ‘622 such that the first plated layer has a surface roughness of about 0.10 μm or more and about 0.27 μm or less to obtain a capacitor which will have improved crack prevention by allowing layer peeling which prevents the propagation of stress from warpage as taught by Hamamori ‘787. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2021/0082623 – [0063] US 2021/0183570 – [0072]
US 2021/0057153 – [0062-0063] US 2021/0272756 – fig. 7
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David M Sinclair/Primary Examiner, Art Unit 2848