DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regards to claim 1,
Claim 1 recites “external electrodes disposed on the surfaces of the multilayer body” which causes the claim to be indefinite as it is unclear to which surfaces (first and second end surface, first and second main surfaces, first and second lateral surfaces) the claim is referencing. Claims 2-11, 17, & 19 are rejected in the same manner based on their dependency on claim 1.
In regards to claim 12,
Claim 12 recites “external electrodes disposed on the surfaces of the multilayer body” which causes the claim to be indefinite as it is unclear to which surfaces (first and second end surface, first and second main surfaces, first and second lateral surfaces) the claim is referencing. Claims 13-16, 18, & 20 are rejected in the same manner based on their dependency on claim 12.
In regards to claim 16,
Claim 16 recites the limitation "the first lateral surface" and “the second lateral surface” in lines 4-5. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 7-14, 16, & 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakano et al. (US 2021/0183581) in view of Kim et al. (US 2021/0082622).
In regards to claim 1,
Nakano ‘581 discloses a multilayer ceramic capacitor, comprising:
a multilayer body (12 – fig. 1; [0028]) including a first main surface and a second main surface (12a & 12b – fig. 1; [0029]) opposed to each other in a lamination direction, a first lateral surface and a second lateral surface (12e & 12f – fig. 1; [0029]) opposed to each other in a width direction, and
a first end surface and a second end surface (12c & 12d – fig. 1; [0029]) opposed to each other in a length direction orthogonal to both the lamination direction and width direction; and
external electrodes (14 & 15 – fig. 1; [0028]) disposed on the surfaces of the multilayer body; wherein
each of the external electrodes includes a base electrode layer (28 – fig. 2; [0051]), a first plated layer (31 – fig. 2; [0055]) on top of the base electrode layer, an adhesive force mitigation layer (26 – fig. 2; [0048]) on top of the base electrode layer, and a second plated layer (32-33 – fig. 2; [0055]) on top of the adhesive force mitigation layer;
the first plated layer is a Cu plated layer ([0055]); and
the second plated layer is connected to the Cu plated layer (electrical connection is present). Nakano ‘581 fails to disclose the adhesive force mitigation layer includes voids in a direction from the second plated layer to the Cu plated layer; the voids are filled with the second plated layer.
Kim ‘622 discloses a multilayer ceramic capacitor, comprising: each of the external electrodes includes a base electrode layer (131a/131b & 132a/132b – fig. 2; [0033]), a first plated layer (131c & 132c – fig. 2; [0033]) on top of the base electrode layer, a second plated layer (131d & 132d – fig. 2; [0033]) on top of the first plated layer, and an adhesive force mitigation layer (141-143 – fig. 2; [0033] or 141’, 142’, & 143 – fig. 6; [0123] or 141”, 142”, & 143 – fig. 8; [0124]) between the first plated layer and the second plated layer while allowing the second plated layer to be in contact with the first plated layer, the adhesive force mitigation layer includes voids (H1/H2 – fig. 6; [0092]) in a direction from the second plated layer to the first plated layer; the voids are filled with the second plated layer (fig. 6; [0092]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct form the capacitor of Nakano ‘581 such that the adhesive force mitigation layer includes voids that are filled with the second plating layer as taught by Kim ‘622 to improved cohesion force and effectively prevent warpage cracks.
In regards to claim 2,
Nakano ‘581 as modified by Kim ‘622 further discloses wherein the second plated layer includes an inner second plated layer (32 – fig. 2; [0055] of Nakano ‘581) and an outer second plated layer (33 – fig. 2; [0055] of Nakano ‘581) on top of the inner second plated layer.
In regards to claim 3,
Nakano ‘581 as modified by Kim ‘622 further discloses the inner second plated layer is a Ni plated layer; and
the outer second plated layer is a Sn plated layer ([0055] of Nakano ‘581).
In regards to claim 4,
Nakano ‘581 as modified by Kim ‘622 further discloses wherein the adhesive force mitigation layer includes an organosilicon compound ([0078-0097] of Nakano ‘581).
In regards to claim 5,
Nakano ‘581 as modified by Kim ‘622 further discloses wherein the organosilicon compound is a multifunctional alkoxysilane ([0078-0097] of Nakano ‘581).
In regards to claim 7,
Nakano ‘581 as modified by Kim ‘622 further discloses wherein the adhesive force mitigation layer is between the first plated layer and the second plated layer and is provided in areas located over outer areas of the first main surface and the second main surface and in areas located over outer areas of the first lateral surface and the second lateral surface (fig. 1-3; [0048-0050] of Nakano ‘581 & fig. 6 & 8 of Kim ‘622), and is not provided in areas located over outer areas of the first end surface and the second end surface (fig. 6 & 8 of Kim ‘622).
In regards to claim 8,
Nakano ‘581 as modified by Kim ‘622 further discloses wherein the dielectric layers include a ceramic material ([0035] of Nakano ‘581).
In regards to claim 9,
Nakano ‘581 as modified by Kim ‘622 further discloses wherein the ceramic material includes:
BaTiO3 as a main component; and
at least one subcomponent selected from a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound ([0035] of Nakano ‘581).
In regards to claim 10,
Nakano ‘581 as modified by Kim ‘622 further discloses wherein the multilayer body further includes an outer layer portion (16a – fig. 2; [0034] of Nakano ‘581); and
the dielectric layers and the outer layer portion include a same ceramic material ([0034-0035] of Nakano ‘581).
In regards to claim 11,
Nakano ‘581 as modified by Kim ‘622 further discloses wherein the adhesive force mitigation layer has a porous structure (fig. 6 & 8 of Kim ‘622).
In regards to claim 12,
Nakano ‘581 discloses a multilayer ceramic capacitor, comprising:
a multilayer body (12 – fig. 1; [0028]) including a first main surface and a second main surface (12a & 12b – fig. 1; [0029]) opposed to each other in a lamination direction, a first side surface and a second side surface (12e & 12f – fig. 1; [0029]) opposed to each other in a width direction, and a first end surface and a second end surface (12c & 12d – fig. 1; [0029]) opposed to each other in a length direction orthogonal to both the lamination direction and width direction; and
external electrodes (14 & 15 – fig. 1; [0028]) disposed on the surfaces of the multilayer body; wherein
each of the external electrodes includes a base electrode layer (28 – fig. 2; [0051]), a first plated layer (31 – fig. 2; [0055]) on top of the base electrode layer, an adhesive force mitigation layer (26 – fig. 2; [0048]) on top of the base electrode layer, and a second plated layer (32-33 – fig. 2; [0055]) on top of the adhesive force mitigation layer;
the first plated layer is a Cu plated layer ([0055]); and
the second plated layer is connected to the Cu plated layer (electrical connection is present). Nakano ‘581 fails to disclose the adhesive force mitigation layer includes voids in a direction from the second plated layer to the Cu plated layer; the second plated layer is disposed in an interior of the voids.
Kim ‘622 discloses a multilayer ceramic capacitor, comprising: each of the external electrodes includes a base electrode layer (131a/131b & 132a/132b – fig. 2; [0033]), a first plated layer (131c & 132c – fig. 2; [0033]) on top of the base electrode layer, a second plated layer (131d & 132d – fig. 2; [0033]) on top of the first plated layer, and an adhesive force mitigation layer (141-143 – fig. 2; [0033] or 141’, 142’, & 143 – fig. 6; [0123] or 141”, 142”, & 143 – fig. 8; [0124]) between the first plated layer and the second plated layer while allowing the second plated layer to be in contact with the first plated layer, the adhesive force mitigation layer includes voids (H1/H2 – fig. 6; [0092]) in a direction from the second plated layer to the first plated layer; the second plated layer is disposed in an interior of the voids (fig. 6; [0092]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct form the capacitor of Nakano ‘581 such that the adhesive force mitigation layer includes voids that are filled with the second plating layer as taught by Kim ‘622 to improved cohesion force and effectively prevent warpage cracks.
In regards to claim 13,
Nakano ‘581 as modified by Kim ‘622 further discloses wherein the second plated layer includes an inner second plated layer (32 – fig. 2; [0055] of Nakano ‘581) and an outer second plated layer (33 – fig. 2; [0055] of Nakano ‘581) on top of the inner second plated layer, the inner second plated layer is a Ni plated layer; and the outer second plated layer is a Sn plated layer ([0055] of Nakano ‘581).
In regards to claim 14,
Nakano ‘581 as modified by Kim ‘622 further discloses wherein the adhesive force mitigation layer includes an organosilicon compound ([0078-0097] of Nakano ‘581), wherein the organosilicon compound is a multifunctional alkoxysilane ([0078-0097] of Nakano ‘581).
In regards to claim 16,
Nakano ‘581 as modified by Kim ‘622 further discloses wherein the adhesive force mitigation layer is between the first plated layer and the second plated layer and is provided in areas located over outer areas of the first main surface and the second main surface and in areas located over outer areas of the first lateral surface and the second lateral surface (fig. 1-3; [0048-0050] of Nakano ‘581 & fig. 6 & 8 of Kim ‘622), and is not provided in areas located over outer areas of the first end surface and the second end surface (fig. 6 & 8 of Kim ‘622).
In regards to claim 19,
Nakano ‘581 as modified by Kim ‘622 further discloses wherein the adhesive force mitigation layer is disposed on the first main surface ([0048] of Nakano ‘581); the multilayer ceramic capacitor is mounted on a circuit board; and the first main surface is a mounting surface ([0031] of Nakano ‘581).
In regards to claim 20,
Nakano ‘581 as modified by Kim ‘622 further discloses wherein the adhesive force mitigation layer is disposed on the first main surface ([0048] of Nakano ‘581); the multilayer ceramic capacitor is mounted on a circuit board; and the first main surface is a mounting surface ([0031] of Nakano ‘581).
Claim(s) 6 & 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakano ‘581 as modified by Kim ‘622 as applied to claims 1 & 12 above, and further in view of Hamamori et al. (US 2018/0082787).
In regards to claims 6 & 15,
Nakano ‘581 as modified by Kim ‘622 fails to disclose wherein the first plated layer has a surface roughness of about 0.10 μm or more and about 0.27 μm or less.
Hamamori ‘787 discloses wherein the surface roughness the external electrode layer adjacent to the adhesive force mitigation layer is a result effective variable, particularly for controlling the surface roughness of adhesive force mitigation layer which will ensure improved crack prevention by allowing layer peeling which prevents the propagation of stress from warpage ([0010], [0019], & [0100]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Nakano ‘581 as modified by Kim ‘622 such that the first plated layer has a surface roughness of about 0.10 μm or more and about 0.27 μm or less to obtain a capacitor which will have improved crack prevention by allowing layer peeling which prevents the propagation of stress from warpage as taught by Hamamori ‘787. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim(s) 1, 12, & 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakano ‘581 in view of Asano et al. (US 2020/0203073).
In regards to claim 1,
Nakano ‘581 discloses a multilayer ceramic capacitor, comprising:
a multilayer body (12 – fig. 1; [0028]) including a first main surface and a second main surface (12a & 12b – fig. 1; [0029]) opposed to each other in a lamination direction, a first lateral surface and a second lateral surface (12e & 12f – fig. 1; [0029]) opposed to each other in a width direction, and
a first end surface and a second end surface (12c & 12d – fig. 1; [0029]) opposed to each other in a length direction orthogonal to both the lamination direction and width direction; and
external electrodes (14 & 15 – fig. 1; [0028]) disposed on the surfaces of the multilayer body; wherein
each of the external electrodes includes a base electrode layer (28 – fig. 2; [0051]), a first plated layer (31 – fig. 2; [0055]) on top of the base electrode layer, an adhesive force mitigation layer (26 – fig. 2; [0048]) on top of the base electrode layer, and a second plated layer (32-33 – fig. 2; [0055]) on top of the adhesive force mitigation layer;
the first plated layer is a Cu plated layer ([0055]); and
the second plated layer is connected to the Cu plated layer (electrical connection is present). Nakano ‘581 fails to explicitly disclose the adhesive force mitigation layer includes voids in a direction from the second plated layer to the Cu plated layer; the voids are filled with the second plated layer.
Asano ‘073 discloses an adhesive force mitigation layer (140/150 – fig. 2, 3, & 5 – [0050-0051]) includes voids (fig. 3) in a direction from a plated layer (124 – fig. 3; [0046]) to the lower electrode layer (122 – fig. 3; [0039]); the voids are filled with the plated layer (fig. 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct form the adhesive force mitigation layer of Nakano ‘581 as taught by Asano ‘073 to obtain a capacitor wherein cracks, poor plating, poor moisture proof reliability, and delamination of an end surface are prevented.
In regards to claim 12,
Nakano ‘581 discloses a multilayer ceramic capacitor, comprising:
a multilayer body (12 – fig. 1; [0028]) including a first main surface and a second main surface (12a & 12b – fig. 1; [0029]) opposed to each other in a lamination direction, a first side surface and a second side surface (12e & 12f – fig. 1; [0029]) opposed to each other in a width direction, and a first end surface and a second end surface (12c & 12d – fig. 1; [0029]) opposed to each other in a length direction orthogonal to both the lamination direction and width direction; and
external electrodes (14 & 15 – fig. 1; [0028]) disposed on the surfaces of the multilayer body; wherein
each of the external electrodes includes a base electrode layer (28 – fig. 2; [0051]), a first plated layer (31 – fig. 2; [0055]) on top of the base electrode layer, an adhesive force mitigation layer (26 – fig. 2; [0048]) on top of the base electrode layer, and a second plated layer (32-33 – fig. 2; [0055]) on top of the adhesive force mitigation layer;
the first plated layer is a Cu plated layer ([0055]); and
the second plated layer is connected to the Cu plated layer (electrical connection is present). Nakano ‘581 fails to disclose the adhesive force mitigation layer includes voids in a direction from the second plated layer to the Cu plated layer; the second plated layer is disposed in an interior of the voids.
Asano ‘073 discloses an adhesive force mitigation layer (140/150 – fig. 2, 3, & 5 – [0050-0051]) includes voids (fig. 3) in a direction from a plated layer (124 – fig. 3; [0046]) to the lower electrode layer (122 – fig. 3; [0039]); the plated layer disposed in an interior of the voids (fig. 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct form the adhesive force mitigation layer of Nakano ‘581 as taught by Asano ‘073 to obtain a capacitor wherein cracks, poor plating, poor moisture proof reliability, and delamination of an end surface are prevented.
In regards to claim 17,
Nakano ‘581 as modified by Asano ‘073 further discloses wherein the adhesive force mitigation layer is disposed on the surfaces of the multilayer body; and the multilayer body is exposed through the voids in the adhesion force mitigation layer (fig. 3 & 5 of Asano ‘073).
In regards to claim 18,
Nakano ‘581 as modified by Asano ‘073 further discloses wherein the adhesive force mitigation layer is disposed on the surfaces of the multilayer body; and the multilayer body is exposed through the voids in the adhesion force mitigation layer (fig. 3 & 5 of Asano ‘073).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY J DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David M Sinclair/Primary Examiner, Art Unit 2847
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