DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 05/11/2026 have been fully considered but they are not persuasive.
On page 7, Applicant argues that the prior arts do not teach “one or more processors including a GPU to process data, wherein the GPU includes a plurality of GPU tiles on a substrate, each GPU tile of the plurality of GPU tiles being a separate chiplet of the GPU, and each GPU tile of the plurality of GPU tiles having a respective tile-based storage”
In response: Danskin disclosed one or more processors including a GPU to process data, wherein the GPU includes a plurality of GPU tiles on a substrate, each GPU tile of the plurality of GPU tiles being a separate chiplet of the GPU, and each GPU tile of the plurality of GPU tiles having a respective tile-based storage, para. [0025], note that it is also to be understood that any number of GPUs may be included in a system, e.g., by including multiple GPUs on a single graphics card or by connecting multiple graphics cards to bus 113. Multiple GPUs may be operated in parallel to generate images for the same display device or for different display devices. Also see para. [0061], note that tiles may be assigned to any number of processing clusters, up to the total number that are present in a particular GPU. In some embodiments, tiles are assigned to fewer than all of the processing clusters. Thus, a GPU can render images using only some of its processing clusters to process pixel threads. Applicant also argues that the tiles presented in Danskin are screen tiles and not GPU tiles. In response, Applicant’s specification recites that “para. [0232] FIG. 15A illustrates geometric data distribution in an apparatus, system, or process. In some embodiments, once geometric data 1510 is assigned a screen-based tile 1515, shown as assignment of geometric data to screen tile-0, screen tile-1, screen tile-2, and screen tile-3, the local data is moved from a distributed data structure to a memory backed local tile data structure 1520 to keep pixel data local to a respective tile of the GPU. This is illustrated in FIG. 15 as distribution from the distributed data storage for screen tile-0, screen tile-1, screen tile-2, and screen tile-3 to the tile-based storage GPU tile-0, GPU tile-1, GPU tile-2, and GPU tile-3.” Thus, the argument presented are not persuasive.
On page 9, Applicant argues that the prior arts do not teach “a mesh shader to operate with the plurality of GPU tiles; wherein the shader is to process data from a GPU tile of the plurality of GPU tiles without transfer of data across GPU tiles of the plurality of GPU tiles.
In response: Danskin disclosed a shader to operate with the plurality of GPU tiles para. [0034], note that geometry module 218 directs programmable processing engines in multithreaded core array 202 to execute vertex and/or geometry shader programs on the vertex data. Para. [0058], the image area can be divided into a number of tiles; wherein the shader is to process data from a GPU tile of the plurality of GPU tiles without transfer of data across GPU tiles of the plurality of GPU tiles, para. [0058], note that the image area can be divided into a number of tiles. Each tile is associated with one of the processing clusters 302 in such a way that the tiles associated with one cluster are scattered across the image area (i.e., at least some of the tiles associated with one processing cluster are not contiguous with one another). In addition to that Nevraev disclosed a mesh shader, para. [0018], note that the present disclosure may move or integrate various shader stages, such as the compute shader, vertex shader, and/or geometry shader, into a single shader stage called a mesh shader. Therefore, the stated argument is taught by the combination of the prior arts.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Danskin et al. (US Publication Number 2012/0026171 A1, hereinafter “Danskin”) in view of Nevraev et al. (US Publication Number 2018/0232912 A1, hereinafter “Nevraev”).
(1) regarding claim 16:
As shown in fig. 1, Danskin disclosed an apparatus (para. [0019], note that computer system 100 includes a central processing unit (CPU) 102 and a system memory 104 communicating via a bus path that includes a memory bridge 105) comprising:
a memory for storage of data, the data including geometric data for graphics processing (para. [0020], note that graphics processing subsystem 112 includes a graphics processing unit (GPU) 122 and a graphics memory 124, which may be implemented, e.g., using one or more integrated circuit devices such as programmable processors, application specific integrated circuits (ASICs), and memory devices);
one or more processors including a graphics processing unit (GPU) to process data (para. [0020], note that GPU 122 may be configured to perform various tasks related to generating pixel data from graphics data supplied by CPU 102 and/or system memory 104 via memory bridge 105 and bus 113, interacting with graphics memory 124 to store and update pixel data, and the like), wherein the GPU includes a plurality of GPU tiles on a substrate, each GPU tile of the plurality of GPU tiles being a separate chiplet of the GPU, and each GPU tile of the plurality of GPU tiles having a respective tile-based storage (para. [0025], note that it is also to be understood that any number of GPUs may be included in a system, e.g., by including multiple GPUs on a single graphics card or by connecting multiple graphics cards to bus 113. Multiple GPUs may be operated in parallel to generate images for the same display device or for different display devices. Also see para. [0061], note that tiles may be assigned to any number of processing clusters, up to the total number that are present in a particular GPU. In some embodiments, tiles are assigned to fewer than all of the processing clusters. Thus, a GPU can render images using only some of its processing clusters to process pixel threads); and
a shader to operate with the plurality of GPU tiles (para. [0034], note that geometry module 218 directs programmable processing engines in multithreaded core array 202 to execute vertex and/or geometry shader programs on the vertex data. Para. [0058], the image area can be divided into a number of tiles);
wherein the shader is to process data from a GPU tile of the plurality of GPU tiles without transfer of data across GPU tiles of the plurality of GPU tiles (para. [0058], note that the image area can be divided into a number of tiles. Each tile is associated with one of the processing clusters 302 in such a way that the tiles associated with one cluster are scattered across the image area (i.e., at least some of the tiles associated with one processing cluster are not contiguous with one another)).
Danskin disclosed most of the subject matter as described as above, such as shader programs, except for specifically teaching a mesh shader.
However, Nevraev disclosed a mesh shader (para. [0018], note that the present disclosure may move or integrate various shader stages, such as the compute shader, vertex shader, and/or geometry shader, into a single shader stage called a mesh shader).
At the time of filing for the invention, it would have been obvious to a person of ordinary skilled in the art to teach a mesh shader. The suggestion/motivation for doing so would have been in order to provide an index compressor that speeds up one or more shader stages by removing processing of at least the primitive connectivity and primitive restart index in a shader stage, which may result in a more efficient per-vertex to per-triangle phase switch (para. [0016]). Therefore, it would have been obvious to combine Danskin with Nevraev to obtain the invention as specified in claim 16.
(2) regarding claim 17:
Danskin further disclosed the apparatus of claim 16, wherein a GPU tile of the plurality of GPU tiles is to obtain geometry data for raster processing, and is to operate on the geometry data locally at the GPU tile (para. [0061], note that tiles may be assigned to any number of processing clusters, up to the total number that are present in a particular GPU. In some embodiments, tiles are assigned to fewer than all of the processing clusters. Thus, a GPU can render images using only some of its processing clusters to process pixel threads).
(3) regarding claim 18:
Danskin further disclosed the apparatus of claim 16, wherein the apparatus is to provide tile-based immediate mode rendering (TBIMR) with the mesh shader (para. [0042], note that as with vertex shader programs and geometry shader programs, rendering applications can specify the pixel shader program to be used for any given set of pixels. Pixel shader programs can be used to implement a variety of visual effects, including lighting and shading effects, reflections, texture blending, procedural texture generation, and so on).
(4) regarding claim 19:
Danskin disclosed most of the subject matter as described as above except for specifically teaching a stream out circuit, wherein the stream out circuit is to read out mesh data from the mesh shader and write the mesh data to the memory in a structure of arrays.
However, Nevraev disclosed a stream out circuit, wherein the stream out circuit is to read out mesh data from the mesh shader and write the mesh data to the memory in a structure of arrays (para. [0019], note that the compressor may select one or more primitives (e.g., triangles) of at least a portion of a mesh formed by a total number of primitives for inclusion within a compressed index buffer block. The one or more primitives may each associated with a number of indices each corresponding to a vertex within the mesh. Also see para. [0047], note that a pre-cull stage such computer shader 92 may both read and write indices)
At the time of filing for the invention, it would have been obvious to a person of ordinary skilled in the art to teach a stream out circuit, wherein the stream out circuit is to read out mesh data from the mesh shader and write the mesh data to the memory in a structure of arrays. The suggestion/motivation for doing so would have been in order to provide an index compressor that speeds up one or more shader stages by removing processing of at least the primitive connectivity and primitive restart index in a shader stage, which may result in a more efficient per-vertex to per-triangle phase switch (para. [0016]). Therefore, it would have been obvious to combine Danskin with Nevraev to obtain the invention as specified in claim 19.
(5) regarding claim 20:
Danskin disclosed most of the subject matter as described as above except for specifically teaching wherein the apparatus is to perform compression of the mesh data from the structure of arrays.
However, Nervaev disclosed wherein the apparatus is to perform compression of the mesh data from the structure of arrays (para. [0045], note that compressor 120 may determine the minimum index of all indices of all primitives of the block. As such, compressor 120 may form the index buffer block 107 based on the determined information including the number of primitives in the index buffer block, the number of indices after reuse in the block, a minimum value of all indices, all indices after reuse biased to the minimum index and fitted into the compression scheme, and/or connectivity information as an array of a number of bytes per primitives).
At the time of filing for the invention, it would have been obvious to a person of ordinary skilled in the art to teach wherein the apparatus is to perform compression of the mesh data from the structure of arrays. The suggestion/motivation for doing so would have been in order to provide an index compressor that speeds up one or more shader stages by removing processing of at least the primitive connectivity and primitive restart index in a shader stage, which may result in a more efficient per-vertex to per-triangle phase switch (para. [0016]). Therefore, it would have been obvious to combine Danskin with Nevraev to obtain the invention as specified in claim 20.
(6) regarding claim 26:
As shown in fig. 2, Danskin disclosed a graphics processor (122, GPU, para. [0020]) comprising:
a substrate (para. [0023], note that GPU is integrated on a single chip i.e. substrate with a bus bridge, such as memory bridge 105);
a plurality of GPU tiles on the substrate, each GPU tile being a separate chiplet, and cach GPU tile having a respective tile-based storage (para. [0025], note that it is also to be understood that any number of GPUs may be included in a system, e.g., by including multiple GPUs on a single graphics card or by connecting multiple graphics cards to bus 113. Multiple GPUs may be operated in parallel to generate images for the same display device or for different display devices); and
a shader to operate with the plurality of GPU tiles (para. [0034], note that geometry module 218 directs programmable processing engines in multithreaded core array 202 to execute vertex and/or geometry shader programs on the vertex data. Para. [0058], the image area can be divided into a number of tiles);
wherein the shader is to process data from a GPU tile of the plurality of GPU tiles without transfer of data across GPU tiles of the plurality of GPU tiles (para. [0058], note that the image area can be divided into a number of tiles. Each tile is associated with one of the processing clusters 302 in such a way that the tiles associated with one cluster are scattered across the image area (i.e., at least some of the tiles associated with one processing cluster are not contiguous with one another).
Danskin disclosed most of the subject matter as described as above, such as shader programs, except for specifically teaching a mesh shader.
However, Nevraev disclosed a mesh shader (para. [0018], note that the present disclosure may move or integrate various shader stages, such as the compute shader, vertex shader, and/or geometry shader, into a single shader stage called a mesh shader).
At the time of filing for the invention, it would have been obvious to a person of ordinary skilled in the art to teach a mesh shader. The suggestion/motivation for doing so would have been in order to provide an index compressor that speeds up one or more shader stages by removing processing of at least the primitive connectivity and primitive restart index in a shader stage, which may result in a more efficient per-vertex to per-triangle phase switch (para. [0016]). Therefore, it would have been obvious to combine Danskin with Nevraev to obtain the invention as specified in claim 26.
(7) regarding claim 27:
Danskin further disclosed the graphics processor of claim 26, wherein a GPU tile of the plurality of GPU tiles is to obtain geometry data for raster processing, and is to operate on the geometry data locally at the GPU tile (para. [0061], note that tiles may be assigned to any number of processing clusters, up to the total number that are present in a particular GPU. In some embodiments, tiles are assigned to fewer than all of the processing clusters. Thus, a GPU can render images using only some of its processing clusters to process pixel threads).
(8) regarding claim 28:
Danskin further disclosed the graphics processor of claim 26, wherein the graphics processor is to provide tile-based immediate mode rendering (TBIMR) with the mesh shader (para. [0042], note that as with vertex shader programs and geometry shader programs, rendering applications can specify the pixel shader program to be used for any given set of pixels. Pixel shader programs can be used to implement a variety of visual effects, including lighting and shading effects, reflections, texture blending, procedural texture generation, and so on).
(9) regarding claim 29:
Danskin disclosed most of the subject matter as described as above except for specifically teaching a stream out circuit, wherein the stream out circuit is to read out mesh data from the mesh shader and write the mesh data to the memory in a structure of arrays.
However, Nevraev disclosed a stream out circuit, wherein the stream out circuit is to read out mesh data from the mesh shader and write the mesh data to the memory in a structure of arrays (para. [0019], note that the compressor may select one or more primitives (e.g., triangles) of at least a portion of a mesh formed by a total number of primitives for inclusion within a compressed index buffer block. The one or more primitives may each associated with a number of indices each corresponding to a vertex within the mesh. Also see para. [0047], note that a pre-cull stage such computer shader 92 may both read and write indices)
At the time of filing for the invention, it would have been obvious to a person of ordinary skilled in the art to teach a stream out circuit, wherein the stream out circuit is to read out mesh data from the mesh shader and write the mesh data to the memory in a structure of arrays. The suggestion/motivation for doing so would have been in order to provide an index compressor that speeds up one or more shader stages by removing processing of at least the primitive connectivity and primitive restart index in a shader stage, which may result in a more efficient per-vertex to per-triangle phase switch (para. [0016]). Therefore, it would have been obvious to combine Danskin with Nevraev to obtain the invention as specified in claim 29.
(10) regarding claim 30:
Danskin disclosed most of the subject matter as described as above except for specifically teaching wherein the apparatus is to perform compression of the mesh data from the structure of arrays.
However, Nervaev disclosed wherein the apparatus is to perform compression of the mesh data from the structure of arrays (para. [0045], note that compressor 120 may determine the minimum index of all indices of all primitives of the block. As such, compressor 120 may form the index buffer block 107 based on the determined information including the number of primitives in the index buffer block, the number of indices after reuse in the block, a minimum value of all indices, all indices after reuse biased to the minimum index and fitted into the compression scheme, and/or connectivity information as an array of a number of bytes per primitives).
At the time of filing for the invention, it would have been obvious to a person of ordinary skilled in the art to teach wherein the apparatus is to perform compression of the mesh data from the structure of arrays. The suggestion/motivation for doing so would have been in order to provide an index compressor that speeds up one or more shader stages by removing processing of at least the primitive connectivity and primitive restart index in a shader stage, which may result in a more efficient per-vertex to per-triangle phase switch (para. [0016]). Therefore, it would have been obvious to combine Danskin with Nevraev to obtain the invention as specified in claim 30.
The proposed rejection of claims 16-20 render obvious the computer-readable storage medium claims 21-24 because these steps occur in the operation of the proposed rejection as discussed above. Thus, the arguments similar to that presented above for claims 16-20 are equally applicable to claims 21-24.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
VanReenen et al. (US Patent Number 10,885,607 B2) disclosed graphics processing unit (GPU) may render image content for portions of an image at different sizes such as at sizes smaller than the size of the portions, and store the smaller-sized image content in system memory. The GPU or some other processing circuitry may retrieve the smaller-sized image content from the system memory, and perform resizing operations to resize the image content to its actual size.
Whitted et al. (US Patent Number 7,414,623 B2) disclosed techniques and tools for rendering procedural graphics are described. For example, an architecture is provided which allows evaluation of geometric, transform, texture, and shading procedures locally for a given set of procedure parameter values. This evaluation is performed in parallel for different parameter values on a single-instruction, multiple-data array to allow parallel processing of a procedure set. In another example, a sampling controller is described which selects sets of parameter points for evaluation based on information in tag maps, rate maps, and parameter maps.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communication from the examiner should be directed to Hilina K Demeter whose telephone number is (571) 270-1676.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, King Y. Poon could be reached at (571) 270- 0728. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HILINA K DEMETER/Primary Examiner, Art Unit 2617
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