DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-6 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication No. 2021/0325538 ("Nishino") in view of U.S. Patent Publication No. 2021/0020793 ("Shinohara").
Regarding claim 2, Nishino discloses a light receiving device comprising:
a light receiving element (211, Fig. 11) configured to generate a first signal in response to reception of a photon (inherent function of a light receiving element, see also paragraph [0064]);
a first transistor (213, Fig. 11) including a first terminal (terminal connected to VS, Fig. 11) coupled to the light receiving element (211, Fig. 11);
a second transistor (311, Fig. 11) including a first terminal coupled to the light receiving element (211, Fig. 11) and the first terminal of the first transistor (terminal of 213 connected to VS, Fig. 11); and
an inverter (214, Fig. 11) coupled to a second terminal of the second transistor (second terminal of 311, Fig. 11),
wherein the first transistor (213, Fig. 11) is a first type (N-type, paragraph [0136]), and the second transistor (311, Fig. 11) is a second type (P-type, paragraph [0136]) that is different from the first type.
Nishino does not disclose that a gate terminal of the first transistor is coupled to a gate terminal of the second transistor.
However, Shinohara discloses a gate terminal of the first transistor (6, Fig. 5) is coupled to a gate terminal of the second transistor (8, Fig. 5).
It would have been an obvious matter of design choice to one of ordinary skill in the art before the effective filing date to couple the gates of two complementary transistors as disclosed by Shinohara in the device of Nishino in order to achieve a specific electrical behavior, for example, strong pull-up and pull-down behavior, or symmetric switching.
Regarding claim 3, Nishino in view of Shinohara discloses the light receiving device according to claim 2, and Nishino further discloses that the gate terminal of the first transistor (213, Fig. 11) is configured to receive a first control signal (for example, signal VG, Fig. 11).
Regarding claim 4, Nishino in view of Shinohara discloses the light receiving device according to claim 3, and Shinohara further discloses that the gate terminal of the [first transistor] (6, Fig. 5) and the second transistor (8, Fig. 5) is configured to receive the first control signal (see Fig. 5, transistors 6 and 8 receive the first control signal from 10, Fig. 5, this is also implicit given the structure claimed in claim 1 where the two transistors have the gates coupled together).
Regarding claim 5, Nishino in view of Shinohara discloses the light receiving device according to claim 4, and Nishino further discloses that the first control signal is a built in self-test (BIST) signal (under the broadest reasonable interpretation, the term “bult-in self-test” is merely a label with no limiting effect given that the claim lacks language to define what makes a BIST signal different than any other signal, therefore, the first control signal being input into transistors, for example VG, Fig. 11 in Nishino or the output of 10, Fig. 5 of Shinohara is a BIST signal).
Regarding claim 6, Nishino in view of Shinohara discloses the light receiving device according to claim 2, and Nishino further discloses that the second terminal of the second transistor (second terminal of 311, Fig. 11) is coupled to a first terminal of a third transistor (212, Fig. 11).
Allowable Subject Matter
Claims 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The invention as claimed, specifically in combination with: the second terminal of the second transistor is coupled to a first terminal of a fourth transistor, is not taught or made obvious by the prior art of record.
Conclusion
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/MONICA T TABA/Examiner, Art Unit 2878