Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “connected in parallel between …” in claim 1 is used by the claim to mean “connected between”. The term is indefinite because the specification does not clearly redefine the term.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CN110620552 (cited by the applicant).
Regarding claim 1, CN110620552 discloses a voltage controlled oscillator (FIG 1) comprising:
a first drive transistor (M1, ¶[0035]) including a first gate terminal connected to a first output node (node between L3 and the drain of M2), the first drive transistor being connected between a second output node (node between L3 and the drain of M1), and a ground node (via M4);
a second drive transistor (M2) connected between the first output node and the ground node, the second drive transistor including a second gate terminal connected to the second output node (see cross-coupled M1 and M2);
a first inductor (L3) connected between the first output node and the second output node;
a second inductor (L4) connected in parallel between a first coupling node (L4 right end) and a second coupling node (L4 left end); and
a first variable capacitance circuit (one pair of the three set of Cvar1-Cvar6) connected in parallel between the first coupling node and the second coupling node,
wherein the second inductor is configured to receive a control voltage and is inductively coupled to the first inductor (L4, L3, Pad6 “the tuning terminal set on the secondary inductor L4…”)(see Extended European Search Report cited by the Applicant).
Regarding claim 2/1, CN110620552 discloses the voltage controlled oscillator wherein the first inductor is configured to receive a power supply voltage (on Pad5) through a center tap node (see FIG 1) included in the first inductor.
Regarding claim 3/1, CN110620552 discloses the voltage controlled oscillator wherein the second inductor is configured to receive the control voltage through a center tap node (see FIG 1) included in the second inductor.
Regarding claim 4/1, CN110620552 discloses the voltage controlled oscillator wherein the first variable capacitance circuit comprises: a first varactor connected between the first coupling node and a first intermediate node (center); and a second varactor connected between the second coupling node and the first intermediate node, and wherein the first intermediate node is configured to receive a first bias voltage (on Pad7-Pad9, the FIG 1 is substantially the same as the applicant’s figure shown in FIG 10).
Regarding claim 5/4/1, CN110620552 discloses the voltage controlled oscillator wherein the first output node and the second output node are configured to respectively output a first output clock and a second output clock having a same frequency and opposite phase with respect to each other.
Regarding claim 6/5/4/1, CN110620552 discloses the voltage controlled oscillator wherein the frequency is based on capacitance of the first variable capacitance circuit.
Regarding claim 7/6/5/4/1, CN110620552 discloses the voltage controlled oscillator wherein: the capacitance of the first variable capacitance circuit is based on the control voltage and the bias voltage.
Regarding claim 8/4/1, CN110620552 implies the voltage controlled oscillator wherein the first varactor comprises a first anode terminal and a first cathode terminal, the second varactor comprises a second anode terminal and a second cathode terminal, the first anode terminal and the second anode terminal are connected to the first intermediate node, the first cathode terminal is connected to the first coupling node, and the second cathode terminal is connected to the second coupling node (the FIG 1 is substantially identical as shown in FIG 10 of this instant application).
Regarding claim 9/4/1, CN110620552 discloses the voltage controlled oscillator further comprising a second variable capacitance circuit (other pair of Cvar1-Cvar6) connected in parallel to the second inductor and the first variable capacitance circuit, the second variable capacitance circuit being connected between the first coupling node and the second coupling node.
Regarding claim 10/9/4/1, CN110620552 discloses the voltage controlled oscillator wherein the second variable capacitance circuit comprises: a third varactor connected between the first coupling node and a second intermediate node; and a fourth varactor connected between the second coupling node and the second intermediate node, and wherein the second intermediate node is configured to receive a second bias voltage different from the first bias voltage (the FIG 1 is substantially the same as the applicant’s figure shown in FIG 10).
Regarding claim 11, CN110620552 discloses a voltage controlled oscillator (FIG 1) configured to receive a control voltage and output first and second output clocks having frequency corresponding to a magnitude of the control voltage, the voltage controlled oscillator comprising:
a first drive transistor (M1) including a first gate terminal connected to a first output node through which the first output clock is output, the first drive transistor being connected between a second output node and a ground node;
a second drive transistor (M2) connected between the first output node and the ground node, the second drive transistor including a second gate terminal connected to the second output node through which the second output clock is output;
an inductance tank circuit (L3) connected between the first output node and the second output node; and
a capacitance tank circuit (Cvar1 – Cvar6) configured to be inductively coupled to the inductance tank circuit, the capacitance tank circuit being configured to operate based on a control voltage that is externally provided (the FIG 1 is substantially the same as the applicant’s figure shown in FIG 10) (L4, L3, Pad6 “the tuning terminal set on the secondary inductor L4…”)(see Extended European Search Report cited by the Applicant).
Regarding claim 12/11, CN110620552 discloses the voltage controlled oscillator wherein the capacitance tank circuit is electrically separated from the first output node and the second output node (FIG 1).
Regarding claim 13/11, CN110620552 discloses the voltage controlled oscillator wherein the inductance tank circuit comprises a first inductor connected between the first output node and the second output node, and the capacitance tank circuit comprises a second inductor connected between a first coupling node and a second coupling node, wherein the second inductor is inductively coupled to the first inductor.
Regarding claim 14/13/11, CN110620552 discloses the voltage controlled oscillator wherein the capacitance tank circuit further comprises a first variable capacitance circuit connected between the first coupling node and the second coupling node, the first variable capacitance circuit being connected in parallel to the second inductor, and the first variable capacitance circuit comprises: a first varactor connected between the first coupling node and a first intermediate node; and a second varactor connected between the second coupling node and the first intermediate node (the FIG 1 is substantially the same as the applicant’s figure shown in FIG 10).
Regarding claim 15/14/13/11, CN110620552 discloses the voltage controlled oscillator (FIG 1) wherein the capacitance tank circuit further comprises a second variable capacitance circuit (other pair of Cvar1 – Cvar6) connected between the first coupling node and the second coupling node, the second variable capacitance circuit being connected in parallel to the second inductor and being connected in parallel to the first variable capacitance circuit, and the second variable capacitance circuit comprises: a third varactor connected between the first coupling node and a second intermediate node; and a fourth varactor connected between the second coupling node and the second intermediate node (the FIG 1 is substantially the same as the applicant’s figure shown in FIG 10).
Regarding claim 16/15/14/13/11, CN110620552 implies the voltage controlled oscillator wherein: the first intermediate node and the second intermediate node are configured to receive bias voltages having different levels with respect to each other (Pad7, Pad8, Pad9).
Regarding claim 17/14/13/11, CN110620552 implies the voltage controlled oscillator wherein the first varactor comprises a first anode terminal and a first cathode terminal, the second varactor comprises a second anode terminal and a second cathode terminal, the first anode terminal and the second anode terminal are connected to the first intermediate node, the first cathode terminal is connected to the first coupling node, and the second cathode terminal is connected to the second coupling node (FIG 1 is substantially the same as the applicant’s figure shown in FIG 10).
Regarding claim 18/13/11, CN110620552 discloses the voltage controlled oscillator (FIG 1) wherein the first inductor is configured to receive a power supply voltage through a first center tap node included in the first inductor, and the second inductor is configured to receive the control voltage through a second center tap node included in the second inductor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN 110620552.
Regarding claim 19, CN110620552 discloses
a voltage controlled oscillator (FIG 1) configured to generate a first output clock and a second output clock based on a control voltage;
wherein the voltage controlled oscillator (FIG 1) comprises
a first inductor (L3) connected between a first output node outputting the first output clock and a second output node outputting the second output clock,
a second inductor (L4) connected between a first coupling node and a second coupling node, the first coupling node and the second coupling node are electrically separated from the first and second output nodes, and the second inductor configured to receive the control voltage and being inductively coupled to the first inductor,
a first varactor (Cvar4, one of the top pair of Cvar3–Cvar4) connected between the first coupling node and a first intermediate node (center of the pair) that is configured to receive a first bias voltage (on Pad7), and
a second varactor (Cvar3) connected between the second coupling node and the first intermediate node.
CN110620552 does not show a phase locked loop including a frequency divider, a frequency phase detector, and a control voltage generator as recited above. As known in the art, such components are typical in a PLL used in many communication devices and other electronic devices. Therefore, it would have been obvious to one of ordinary skill in the art to use the VCO shown in CN110620552 into a PLL as intended.
Regarding claim 20/19, the modification of CN110620552 discloses the phase locked loop wherein the voltage controlled oscillator further comprises: a third varactor (one of second set of Cvar2 and Cvar5) connected between the first coupling node and a second intermediate node configured to receive a second bias voltage (on Pad8); and a fourth varactor (other one of the second set) connected between the second coupling node and the second intermediate node (FIG 1 is substantially the same as the applicant’s figure shown in FIG 10, see three pairs of variable capacitors).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chang (US 2025/0125771) discloses a VCO showing LC differential oscillator with a control voltage connected to a center tap of inductor and variable capacitors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joseph Chang whose telephone number is (571)272-1759. The examiner can normally be reached M-F 7:00- 17:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH CHANG/Primary Examiner, Art Unit 2849