DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the amendment filed 8/10/2026 Claims 1-20 are pending and are under examination.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. In this instant, the newly added limitations “wherein a maximum rated operating voltage of each high voltage switch is at least equal to the second high voltage, and a maximum rated operating voltage of each low voltage threshold switch and each medium voltage switch is less than the second high voltage” of independent claims 1, 9 and 17 was not described in the specification in such a way one skilled in the art were able to make and use of the invention at the time the application was filed.
Claims 2-8, 10-16 and 18-20 are also rejected under 35USC 112, first paragraph because of the technical deficiencies of claims 1, 9 and 17.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-11, 13-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kubota et al. (USP 6,157,361).
Regarding claims 1 and 17, Kubota et al.’s figure 4 shows A level shifter circuit, comprising: an input circuit (Q01, Q02) comprising a plurality of low voltage threshold switches (Q01, Q02 are switches capable of handling low switching voltage) and configured to receive an input voltage (IN) and to generate a second voltage (LO2), wherein the second voltage varies between a first low voltage (0V) and a first high voltage (5V); an output circuit (LS1j) comprising a first plurality of high voltage switches (transistors within LS1j are capable of handling high voltage) and configured to receive the second voltage and to generate a third voltage (L12), wherein the third voltage varies between the first low voltage (0V) and a second high voltage (10V); and a buffer circuit (LS2j) , the buffer circuit being configured to receive the third voltage and to generate a buffer circuit output voltage (OUT), wherein the buffer circuit output voltage varies between a second low voltage (-8V) and the second high voltage (10V); wherein each N type switch of the output circuit and the buffer circuit is either a medium voltage switch or a low voltage switch (since the N type switches Q11, Q12 are operated with a potential difference of 10V; and the N type switches Q23 and Q24 are operated with a potential voltage difference of 18V (10v-(-8v)=18v), thus, the N type switches are either a medium voltage switch or low voltage switch), and wherein a maximum rated operating voltage of each high voltage switch is at least equal to the second high voltage (since the switches Q11, Q12, Q13 and Q14 are operated with a potential difference of 10V (10V is the second high voltage), thus, their maximum rated is least at 10V. It is also noted that Kubota et al. is silent as to the transistors Q11, Q12, Q13, Q14 are having different sizes/switching threshold voltages, thus, it is assumed that the transistors Q11-Q14 are having the same size/switching threshold voltage), and a maximum rated operating voltage of each low voltage threshold switch and each medium voltage switch is less than the second high voltage (low voltage threshold switches are Q01 and Q02 and they are operated with a potential difference of 5V (5V is less than the second high voltage of 10V), thus, their maximum rated is less than 10V); as called for in claims 1 and 17.
Regarding claims 2 and 18, wherein the second high voltage (10V) is greater than the first low voltage (0V), and wherein the first high voltage (5V) is less than the second high voltage (10V).
Regarding claims 3 and 19, wherein the second low voltage is greater than the first low voltage (the absolute value of /-8/ is greater the /0/).
Regarding claim 5, wherein the output circuit further comprises a second plurality of low voltage switches (Q11, Q12 are capable of handling voltage varies between 0v to 5V).
Regarding claim 6, wherein the first high voltage (5V) is greater than the first low voltage (0V) and is less than the second high voltage (10V).
Regarding claim 7, wherein the buffer circuit comprises a plurality of medium voltage switches (transistors within the buffer circuits are capable of handling medium voltage).
Regarding claim 8, wherein each P type switch of the output circuit and the buffer circuit is a high voltage switch, (transistors Q13, Q14, Q21, Q22) are capable of handling high voltage of 10V and 18V).
Regarding claim 9, Kubota et al. reference shows An array circuit, comprising: an array of devices, wherein a plurality of devices of the array (ARY; figure 8) each comprise at least one high voltage switch (figure 9); a controller (11) configured to generate a plurality of first control signals for controlling the array of devices; and an array of level shifters (LS11-LS1n; LS21 to LS2n), each level shifter configured to receive one of the first control signals from the controller as an input voltage, to generate one of a plurality of second control signals as a level shifter output voltage, and to provide the level shifter output voltage to one of the devices of the array of devices, wherein the level shifters each comprise: an input circuit (Q01, Q02) comprising a plurality of low voltage threshold switches (Q01, Q02 are switches capable of handling low switching voltage) and configured to receive an input voltage (IN) and to generate a second voltage (LO2), wherein the second voltage varies between a first low voltage (0V) and a first high voltage (5V); an output circuit (LS1j) comprising a first plurality of high voltage switches (transistors within LS1j are capable of handling high voltage) and configured to receive the second voltage and to generate a third voltage (L12), wherein the third voltage varies between the first low voltage (0V) and a second high voltage (10V); and a buffer circuit (LS2j) , the buffer circuit being configured to receive the third voltage and to generate a buffer circuit output voltage (OUT), wherein the buffer circuit output voltage varies between a second low voltage (-8V) and the second high voltage (10V); wherein each N type switch of the output circuit and the buffer circuit is either a medium voltage switch or a low voltage switch (since the N type switches Q11, Q12 are operated with a potential difference of 10V; and the N type switches Q23 and Q24 are operated with a potential voltage difference of 18V (10v-(-8v)=18v), thus, the N type switches are either a medium voltage switch or low voltage switch), and wherein a maximum rated operating voltage of each high voltage switch is at least equal to the second high voltage (since the switches Q11, Q12, Q13 and Q14 are operated with a potential difference of 10V (10V is the second high voltage), thus, their maximum rated is least at 10V. It is also noted that Kubota et al. is silent as to the transistors Q11, Q12, Q13, Q14 are having different sizes/switching threshold voltages, thus, it is assumed that the transistors Q11-Q14 are having the same size/switching threshold voltage), and a maximum rated operating voltage of each low voltage threshold switch and each medium voltage switch is less than the second high voltage (low voltage threshold switches are Q01 and Q02 and they are operated with a potential difference of 5V (5V is less than the second high voltage of 10V), thus, their maximum rated is less than 10V); as called for in claim 9.
Regarding claim 10, wherein the second high voltage (10V) is greater than the first low voltage (0V), and wherein the first high voltage (5V) is less than the second high voltage (10V).
Regarding claim 11, wherein the second low voltage is greater than the first low voltage (the absolute value of /-8/ is greater the /0/).
Regarding claim 13, wherein the output circuit further comprises a second plurality of low voltage switches (Q11, Q12 are capable of handling voltage varies between 0v to 5V).
Regarding claim 14, wherein the first high voltage (5V) is greater than the first low voltage (0V) and is less than the second high voltage (10V).
Regarding claim 15, wherein the buffer circuit comprises a plurality of medium voltage switches (transistors within the buffer circuits are capable of handling medium voltage).
Regarding claim 16, wherein each P type switch of the output circuit and the buffer circuit is a high voltage switch, (transistors Q13, Q14, Q21, Q22) are capable of handling high voltage of 10V and 18V).
Claim(s) 1-2, 4-6, 8-10, 12-18 and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Henmi (US 2013/0162294).
Regarding claims 1 and 17, Henmi et al.’s figure 4 shows A level shifter circuit, comprising: an input circuit (110) comprising a plurality of low voltage threshold switches (transistors within 110 are switches capable of handling low switching voltage) and configured to receive an input voltage (DI) and to generate a second voltage (DIB), wherein the second voltage varies between a first low voltage (Vss) and a first high voltage (VDD1); an output circuit (N1, N2, P1, P2, P5, P6) comprising a first plurality of high voltage switches (transistors are capable of handling high voltage) and configured to receive the second voltage and to generate a third voltage (ND/NU), wherein the third voltage varies between the first low voltage (Vss) and a second high voltage (VDD2); and a buffer circuit (P3, P4, N3, N4) , the buffer circuit being configured to receive the third voltage and to generate a buffer circuit output voltage (D0), wherein the buffer circuit output voltage varies between a second low voltage (Vss) and the second high voltage (VDD2); wherein each N type switch of the output circuit and the buffer circuit is either a medium voltage switch or a low voltage switch (since the N type switches N1, N2 are operated with a potential difference of VSS-VDD2; and the N type switches N3, N4 are operated with a potential voltage difference of VSS-VDD2, thus, the N type switches are either a medium voltage switch or low voltage switch), and wherein a maximum rated operating voltage of each high voltage switch is at least equal to the second high voltage (since the switches N1, N2, P1, P2, P5, P6 are operated with a potential difference of Vss-VDD2 (VDD2 is the second high voltage), thus, their maximum rated is least at VDD2. Also, Henmi is also silent as to the transistors N1, N2, P1, P2, P5 and P6 are having different sizes/threshold switching voltages, thus, it is assumed that all the transistors N1, N2, P1, P2, P5 and P6 are having the same size/threshold switching voltage), and a maximum rated operating voltage of each low voltage threshold switch and each medium voltage switch is less than the second high voltage (low voltage threshold switches are the transistors within 110 and they are operated with a potential difference of VSS-VDD1 (VDD1 is less than the second high voltage of VDD2), thus, their maximum rated is less than VDD2; Also, Henmi is also silent as to the transistors within 110 are having different size/threshold switching voltage, thus, it is assumed that all the transistors N1, N2, P1, P2, P5 and P6 are having the same size/threshold switching voltage); as called for in claims 1 and 17.
Regarding claims 2 and 18, wherein the second high voltage (VDD2) is greater than the first low voltage (Vss), and wherein the first high voltage (VDD1) is less than the second high voltage (VDD2).
Regarding claims 4 and 20, wherein the second low voltage is equal to the first low voltage (Vss).
Regarding claim 5, wherein the output circuit further comprises a second plurality of low voltage switches (N1, N2, P1, P2, P5, P6 are capable of handling voltage varies between Vss to VDD1).
Regarding claim 6, wherein the first high voltage (VDD1) is greater than the first low voltage (Vss) and is less than the second high voltage (VDD2).
Regarding claim 8, wherein each P type switch of the output circuit and the buffer circuit is a high voltage switch, (transistors P2, P1; P3, P4) are capable of handling high voltage of VDD2).
Regarding claim 9, Henmi et al. reference shows An array circuit, comprising: an array of devices, wherein a plurality of devices of the array (340; figure 9) each comprise at least one high voltage switch (pixel within display panel made of switches); a controller (310) configured to generate a plurality of first control signals for controlling the array of devices; and an array of level shifters (327), each level shifter configured to receive one of the first control signals from the controller as an input voltage, to generate one of a plurality of second control signals as a level shifter output voltage, and to provide the level shifter output voltage to one of the devices of the array of devices, wherein the level shifters each comprise an input circuit (110) comprising a plurality of low voltage threshold switches (transistors within 110 are switches capable of handling low switching voltage) and configured to receive an input voltage (DI) and to generate a second voltage (DIB), wherein the second voltage varies between a first low voltage (Vss) and a first high voltage (VDD1); an output circuit (N1, N2, P1, P2, P5, P6) comprising a first plurality of high voltage switches (transistors are capable of handling high voltage) and configured to receive the second voltage and to generate a third voltage (ND/NU), wherein the third voltage varies between the first low voltage (Vss) and a second high voltage (VDD2); and a buffer circuit (P3, P4, N3, N4) , the buffer circuit being configured to receive the third voltage and to generate a buffer circuit output voltage (D0), wherein the buffer circuit output voltage varies between a second low voltage (Vss) and the second high voltage (VDD2); wherein each N type switch of the output circuit and the buffer circuit is either a medium voltage switch or a low voltage switch (since the N type switches N1, N2 are operated with a potential difference of VSS-VDD2; and the N type switches N3, N4 are operated with a potential voltage difference of VSS-VDD2, thus, the N type switches are either a medium voltage switch or low voltage switch), and wherein a maximum rated operating voltage of each high voltage switch is at least equal to the second high voltage (since the switches N1, N2, P1, P2, P5, P6 are operated with a potential difference of Vss-VDD2 (VDD2 is the second high voltage), thus, their maximum rated is least at VDD2. Also, Henmi is also silent as to the transistors N1, N2, P1, P2, P5 and P6 are having different sizes/threshold switching voltages, thus, it is assumed that all the transistors N1, N2, P1, P2, P5 and P6 are having the same size/threshold switching voltage), and a maximum rated operating voltage of each low voltage threshold switch and each medium voltage switch is less than the second high voltage (low voltage threshold switches are the transistors within 110 and they are operated with a potential difference of VSS-VDD1 (VDD1 is less than the second high voltage of VDD2), thus, their maximum rated is less than VDD2; Also, Henmi is also silent as to the transistors within 110 are having different size/threshold switching voltage, thus, it is assumed that all the transistors N1, N2, P1, P2, P5 and P6 are having the same size/threshold switching voltage); as called for in claim 9.
Regarding claim 10, wherein the second high voltage (VDD2) is greater than the first low voltage (VSS), and wherein the first high voltage (VDD1) is less than the second high voltage (VDD2).
Regarding claim12, wherein the second low voltage is equal to the first low voltage (Vss).
Regarding claim 13, wherein the output circuit further comprises a second plurality of low voltage switches (N3, N4, P3, P4 are capable of handling low voltage).
Regarding claim 14, wherein the first high voltage (VDD1) is greater than the first low voltage (VSS) and is less than the second high voltage (VDD2).
Regarding claim 15, wherein the buffer circuit comprises a plurality of medium voltage switches (transistors within the buffer circuits are capable of handling medium voltage).
Regarding claim 16, wherein each P type switch of the output circuit and the buffer circuit is a high voltage switch, (transistors P2, P1; P3, P4) are capable of handling high voltage of VDD2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 12 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kubota et al. (USP 6,157,361).
Regarding claims 4, 12 and 20, Kubota et al. references discloses a level shifter circuit comprising all the aspects of the present invention except for the first low voltage is equal to the second low voltage as called for in claims 4, 12 and 20. It is a common knowledge in a field of level shifter circuits, an output of the level shifters provide signals between different voltage domains, protecting low-voltage components from damage, enabling the use of high-voltage devices, ensuring proper signal recognition, and allowing for efficient power management in systems with mixed-voltage requirements. This is achieved by translating a low-voltage input to a high-voltage output or vice versa, thereby creating a reliable and compatible interface between disparate circuit parts. The specific translated voltage levels depends on the operated high power supply voltage and low power supply voltage. Thus, by choosing the low power supply to be equal between level shifters would have been an obvious choice to ensure a reliable and compatible interface between disparate circuit parts. Therefore, outside of any non-obvious results, the obviousness of having the first and second low voltages equal will not be patentable under 35USC 103.
Response to Arguments
Applicant's arguments filed 7/6/2026 have been fully considered but they are not persuasive. Regarding the rejection of claims 1-3, 5-11 and 13-19 as being anticipated by Kubota (USP 6,157,361), applicant argues that Kubota fails to teach or disclose “wherein each N type switch of the output circuit and the buffer circuit is either a medium voltage switch or a low voltage switch, and wherein a maximum rated operating voltage of each high voltage switch is at least equal to the second high voltage, and a maximum rated operating voltage of each low voltage threshold switch and each medium voltage switch is less than the second high voltage” found not persuasive. Since the N type switches Q11, Q12 are operated with a potential difference of 10V; and the N type switches Q23 and Q24 are operated with a potential voltage difference of 18V (10v-(-8v)=18v), thus, the N type switches are either a medium voltage switch or low voltage switch. Furthermore, a maximum rated operating voltage of each high voltage switch is at least equal to the second high voltage (since the switches Q11, Q12, Q13 and Q14 are operated with a potential difference of 10V (10V is the second high voltage), thus, their maximum rated is least at 10V. It is also noted that Kubota et al. is silent as to the transistors Q11, Q12, Q13, Q14 are having different sizes/switching threshold voltages, thus, it is assumed that the transistors Q11-Q14 are having the same size/switching threshold voltage.
Regarding the rejection of claims 1-2, 4-10, 12-18 and 20 as being anticipated by Henmi et al. (US 2013/0162294), applicant argues that Henmi does not disclose “wherein each N type switch of the output circuit and the buffer circuit is either a medium voltage switch or a low voltage switch, and wherein a maximum rated operating voltage of each high voltage switch is at least equal to the second high voltage, and a maximum rated operating voltage of each low voltage threshold switch and each medium voltage switch is less than the second high voltage found not persuasive. Since the N type switches N1, N2 are operated with a potential difference of VSS-VDD2; and the N type switches N3, N4 are operated with a potential voltage difference of VSS-VDD2, thus, the N type switches are either a medium voltage switch or low voltage switch. Furthermore, a maximum rated operating voltage of each high voltage switch is at least equal to the second high voltage (since the switches N1, N2, P1, P2, P5, P6 are operated with a potential difference of Vss-VDD2 (VDD2 is the second high voltage), thus, their maximum rated is least at VDD2. Also, Henmi is also silent as to the transistors N1, N2, P1, P2, P5 and P6 are having different sizes/threshold switching voltages, thus, it is assumed that all the transistors N1, N2, P1, P2, P5 and P6 are having the same size/threshold switching voltage). The rejection is deemed proper. Claims 1-2, 4-6, 9-10, 12-18 and 20 remain rejected.
Conclusion
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/TUAN T LAM/Primary Examiner, Art Unit 2842 8/21/2026
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