DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 08/12/2024, is/are in compliance with the provisions 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 16-17 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Jeong et al. (US 20250048739) herein referred to as Jeong.
As to claim 1, Jeong teaches a thin film transistor comprising:
an active layer ([0053] “the thin film transistor TFT may include an active layer 130”); and
a gate electrode ([0053] “a gate electrode 150”) spaced apart from the active layer (130),
the gate electrode (150) at least partially overlapping with the active layer (Fig 3, [0053] “A gate electrode 150 spaced apart from the active layer 130 and partially overlapping the active layer 130”) wherein
the active layer (130) includes:
a channel area (130n) at least partially overlapping with the gate electrode in a plan view ([0063] The active layer 130 may include a channel area 130n partially overlapping the gate electrode 150 in a plane);
a source area connected to one side of the channel area ([0063] “a source area 130a connected to one side of the channel area 130n”);
a drain area connected to another side of the channel area ([0063] “a drain area 130b connected to the other side of the channel area 130n”); and
an active hole ([0069] In FIGS. 1 and 3, an active hole 135) penetrating through opposite sides of the active layer (130),
the active hole (Fig. 3, 135) including a first active hole, wherein
at least a portion of the first active hole (135) overlaps with the gate electrode (150), wherein the first active hole includes:
a first area overlapping with the gate electrode (Annotated 1st area Jeong, Fig 3); and
a second area (Annotated 2nd area Jeong, Fig 3)that does not overlap with the gate electrode (150), and wherein
an area of the second area is greater than or equal to an area of the first area (Annotated 1st and 2nd area Jeong, Fig 3).
PNG
media_image1.png
408
600
media_image1.png
Greyscale
As to claim 2, Jeong teaches the thin film transistor of claim 1, as discussed above, and further discloses wherein
a direction parallel to a shortest line connecting the source area and the drain area is a first direction (Annotated Jeong Fig. 3, x-direction), and
a direction perpendicular to the first direction is a second direction (Annotated Jeong Fig. 3, y- direction),, and wherein
a width of the first active hole in the second direction decreases as a distance away from the second area in the first direction increases (Fig. 3, tapered hole 135).
As to claim 16, Jeong teaches the thin film transistor of claim 1, as discussed above, and further discloses:
a source electrode in contact with the source area through a contact hole ([0058] “In FIGS. 1, 2, and 3, the source electrode 160) ; and
a drain electrode spaced apart from the source electrode and in contact with the drain area through a contact hole ([0058] “ In FIGS. 1, 2, and 3, the source electrode 160 and the drain electrode 170 are disposed on the gate insulation layer 140).
As to claim 17, Jeong teaches a display apparatus comprising:
the thin film transistor of claim 1: as discussed above, and further discloses:
([0008] Accordingly, embodiments of the present disclosure are directed to a thin film transistor substrate and a display apparatus).
Allowable Subject Matter
Claim 18 is allowed. The following is an examiner’s statement of reasons for allowance: The primary reference Jeong et al. (US 20250048739) separately or as combined do not teach all of the limitations of claim 18.
As to claim 18, Jeong teaches a thin film transistor comprising:
an active layer ([0053] “the thin film transistor TFT may include an active layer 130”); disposed on a substrate ([0053] “ base substrate 110”);
a gate electrode ([0053] “a gate electrode 150”) overlapping with the active layer (130);
a source electrode electrically connected to the active layer ([0099] In FIGS. 2 and 3, the source electrode 160 and the drain electrode 170 are connected to the active layer 130);
a drain electrode electrically connected to the active layer ([0099] In FIGS. 2 and 3, the source electrode 160 and the drain electrode 170 are connected to the active layer 130); and
at least one hole (135) in the active layer (130), wherein
the at least one hole at least partially overlaps with an edge of the gate electrode (Annotated 1st area Jeong, Fig 3), wherein
the at least one hole includes two holes penetrating through the active layer (Fig. 4, (135)), wherein
Jeong does not teach:
the two holes overlap with opposite edges of the gate electrode, and wherein
the two holes have tapered shapes that point towards each other.
The plurality of holes (135) overlap only on one side of the gate electrode. (See Fig. 4) The plurality of holes (135) do not have tapered shapes that point towards each other. (See Fig. 4)
Claim(s) 19-20 is/are allowable at least because they depend from allowed claim 18.
Claim(s) 3-15 is/are objected to as being dependent upon a rejected base claim 1, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on (571) 272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
