DETAILED ACTION
This action is responsive to the following communications: the Application filed August 12, 2024.
Claims 1-20 are pending. Claims 1, 11 and 14 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka et al. (US 5,007,024).
Regarding independent claim 1, Tanaka et al. disclose a memory comprising a sensing amplifier (SA, figure 3) and a plurality of memory cells (14 and 12, figure 3), wherein the plurality of memory cells are coupled to a bit line (BT and DB, figure 3), the bit line (BT, figure 3) is connected to the SA (SA, figure 3), and the SA includes a first transistor (27, figure 3) and a second transistor (23, figure 3); wherein the first transistor is coupled with a first voltage source (VSS, figure 3) of the SA or a second voltage source (VCC, figure 3) of the SA; and wherein the second transistor (23, figure 3) is coupled with the bit line (BT, figure 3) and capable of being controlled with a gate voltage of not less than 1.5V (H= A GATE VOLTAGE >1.5V)
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Regarding claim 14, Tanaka et al. disclose a memory system comprising a controller and a memory, wherein the controller is coupled to the memory to control the memory to store data (30, figure 4 (FIG. 3, when in the read mode, the read/write signal RW being set at "H" level in this mode. A read operation performed by the circuit shown in FIG. 3 will now be described hereinafter, with reference to the above-mentioned timing chart)), wherein the memory includes a sensing amplifier (SA) and a plurality of memory cells, the plurality of memory cells are coupled to a bit line, the bit line is connected to the SA, and the SA includes a first transistor and a second transistor; wherein the first transistor is coupled with a first voltage source of the SA or a second voltage source of the SA; and wherein the second transistor is coupled with the bit line and capable of being controlled with a gate voltage of not less than 1.5V (see rejection of claim 1 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US 5,007,024) in view of Pathak et al. (US 5,680,346).
Regarding claim 9, Tanaka et al. disclose the limitation of claim 1.
However, Tanaka et al. are silent with respect to wherein a thickness of a gate oxide layer of the second transistor is at least twice that of a gate oxide layer of the first transistor.
Pathak et al. disclose wherein a thickness of a gate oxide layer of the second transistor is at least twice that of a gate oxide layer of the first transistor (see paragraph and figure 2 below).
(d) read select means for selective connection of said non-volatile memory cell to said read bitline, said read select means being connected in series between said source region of said floating gate transistor of said non-volatile memory cell and said read bitline such that said source region of said floating gate transistor of said non-volatile memory call forms a non-branching connection to said read select means, said read select means having a control gate disposed over a third oxide layer and being distinct from both said floating gate and said control gate of said floating gate transistor for controlling, in cooperation with said control gate of said floating gate transistor, the passage of electric current through said non-volatile memory cell and said read select means, said second oxide layer being at least twice as thick as said third oxide layer, said control gate of said read select means being drivable separately from said control gate of said floating gate transistor, and said read select means being effective for enabling reading of said memory cell in response to a read signal on the control gate of said read select means.
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Since Tanaka et al. and Pathak et al. are both from the same field of endeavor, the purpose disclosed by Pathak et al. would have been recognized in the pertinent art of Tanaka et al.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Tanaka et al. to teaching of Pathak et al. for purpose of using the read bitline is ground, and programmed information is programmable into the non-volatile memory cell for storage and retention.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US 5,007,024) in view of ONUKI et al. (US 2022/0036928).
Regarding claim 10, Tanaka et al. disclose the limitation of claim 1.
However, Tanaka et al. are silent with respect wherein the plurality of memory cells include a first memory cell, the bit line includes a first bit line, the first memory cell includes a transistor structure and a capacitor structure, and the transistor structure is coupled to the first bit line and the capacitor structure, respectively.
ONUKI et al. disclose wherein the plurality of memory cells include a first memory cell, the bit line includes a first bit line, the first memory cell includes a transistor structure and a capacitor structure, and the transistor structure is coupled to the first bit line and the capacitor structure, respectively (see figure below).
Since Tanaka et al. and ONUKI et al. are both from the same field of endeavor, the purpose disclosed by ONUKI et al. would have been recognized in the pertinent art of Tanaka et al.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Tanaka et al. to teaching of ONUKI et al. for purpose of using the read bitline is ground, and programmed information is programmable into the non-volatile memory cell for storage and retention.
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Allowable Subject Matter
Claims 2-8 and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 2, the prior made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the second transistor includes a first N type metal oxide semiconductor (N-MOS transistor), a second N-MOS transistor, a third N-MOS transistor, and a fourth N-MOS transistor; wherein the bit line includes a first bit line and a second bit line, the first N-MOS transistor and the fourth N-MOS transistor are respectively coupled to the first bit line, and the second N-MOS transistor and the third N-MOS transistor are respectively coupled to the second bit line; and the first N-MOS transistor and the second N-MOS transistor are controlled with a same gate voltage, and the third N-MOS transistor and the fourth N-MOS transistor are controlled with a same gate voltage in combination with other limitations thereof as is recited in the claim. Claim 3 depends on claim 2.
Regarding claim 4, the prior made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of the plurality of memory cells and a first bonding structure are formed in the first semiconductor structure, and the SA and a second bonding structure are formed in the second semiconductor structure, the first semiconductor structure and the second semiconductor structure are bonded to each other through the first bonding structure and the second bonding structure in combination with other limitations thereof as is recited in the claim. Claim 5-8 depend on claim 4.
Regarding claim 15, the prior made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the second transistor includes a first N type metal oxide semiconductor (N-MOS transistor), a second N-MOS transistor, a third N-MOS transistor, and a fourth N-MOS transistor; wherein the bit line includes a first bit line and a second bit line, the first N-MOS transistor and the fourth N-MOS transistor are respectively coupled to the first bit line, and the second N-MOS transistor and the third N-MOS transistor are respectively coupled to the second bit line; and the first N-MOS transistor and the second N-MOS transistor are controlled with a same gate voltage, and the third N-MOS transistor and the fourth N-MOS transistor are controlled with a same gate voltage in combination with other limitations thereof as is recited in the claim. Claim 16 depends on claim 15.
Regarding claim 17, the prior made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the memory includes a first semiconductor structure and a second semiconductor structure, the plurality of memory cells and a first bonding structure are formed in the first semiconductor structure, and the SA and a second bonding structure are formed in the second semiconductor structure, the first semiconductor structure and the second semiconductor structure are bonded to each other through the first bonding structure and the second bonding structure in combination with other limitations thereof as is recited in the claim. Claims 18-20 depends on claim 17.
Claims 11-13 are allowed.
Regarding independent claim 11, the prior art does not teach or suggest the claimed invention having “wherein the memory includes a sensing amplifier (SA), and the method comprises: providing a gate voltage of less than 1.5V to a first transistor in the SA to turn on the first transistor; and providing a gate voltage of not less than 1.5V to a second transistor in the SA to turn on the second transistor”, in combination of other limitations thereof as recited in the claim.
Regarding claims 12-13, the claims have been found allowable due to their dependencies to claim 11 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MINH D DINH whose telephone number is (571)270-5375. The examiner can normally be reached Monday to Friday 8:00am 5:00pm.
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/MINH D DINH/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827