Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Ishida (US 20170181282 A1).
Regarding claim 1, Ishida teaches in figure 3 a circuit body implemented by a multilayer flexible substrate ([0052]; wherein printed wiring board 1 is multilayered and flexible),
the multilayer flexible substrate including
a plurality of conductor layers having a plurality of conductor patterns for implementing a circuit configuration (wiring layers 9 and 11 and conductor layer of pads 15 and 17), and
a plurality of insulating layers (substrates 3, including 31-34, and top layer of adhesive 4 and coverlay 5) arranged in a manner of sandwiching the plurality of conductor layers therebetween (see figure 3), wherein
in each of the plurality of the conductor patterns, a contact portion (pads 15a) is provided in a first conductor layer (conductor layer of pads 15 and 17) adjacent to a first insulating layer (4 and 5) among the plurality of conductor layers, and is exposed to an outside through an opening provided in the first insulating layer (opening in 4 and 5) constituting a mounting face of the flexible substrate (top surface of 5) among the plurality of insulating layers to be connected to an external terminal,
a plurality of the contact portions (pads 15 and 17) include
a first contact portion (15a) belonging to the conductor pattern, the conductor pattern extending across the first conductor layer and a second conductor layer different from the first conductor layer (Figure 4B; wherein 15a is connected to wiring layers 9 by via 24), and
a second contact portion (17a) that is different from the first contact portion and that is located at a position farther from a terminal end of the flexible substrate than the first contact portion (see figure 1; [0078]; wherein pads 17a are in a rear array), and
in the second conductor layer, a dummy pattern (Figure 4B; patterns 9a’ and 11a’, and R1 and R2), which is the conductor pattern that does not contribute to the circuit configuration ([0100]; wherein the patterns are not electrically connected to 15a and 9), is arranged on at least one of a corresponding position corresponding to the first contact portion and a vicinity of the corresponding position in a thickness direction of the flexible substrate (see figure 4B; [0100]; wherein portions 9a’ and 11a’ maintain a uniform thickness of the wiring board 1).
Regarding claim 2, Ishida teaches in figure 4B a circuit body (1), wherein
in a case that the mounting face around a peripheral edge of the opening portion where the second contact portion is exposed is defined as a reference face position (surface of 5),
the dummy pattern is arranged such that a difference between an interval in the thickness direction between the first contact portion and the reference face position and an interval in the thickness direction between the second contact portion and the reference face position is close to zero ([0100]; wherein portions 9a’ and 11a’, corresponding to pads 15a and 17a, maintain a uniform thickness of the wiring board 1).
Regarding claim 3, Ishida teaches in figure 1 a circuit body (1), wherein
the dummy pattern is arranged so as to sandwich the corresponding position in a plate face direction of the flexible substrate (wherein R1 and R2 of the dummy pattern sandwich the corresponding position).
Regarding claim 4, Ishida teaches in figure 24 a connector-attached circuit body comprising:
a circuit body (1); and
a connector (50) that is to be mounted on the mounting face of the circuit body and has a plurality of the external terminals (54) to be connected to the plurality of the contact portions (15 and 17).
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure Miya (JP 2007213998 A), Kim (US 20190199025 A1), and Lee (US 20180063962 A1).
Miya teaches a circuit body with multiple conductor layers, rows of contact points, and a connector mounted on the circuit body.
Kim teaches a multilayer circuit body with rows of circuit patterns, including corresponding dummy patterns, to be attached to a connector at contact points.
Lee teaches a circuit board with a flexible circuit with a circuit pattern of pads in a position sandwiched by dummy patterns, with the pads capable of electrical connection to another electrical component.
The above references are considered of particular relevance to the claimed invention but cannot
be considered to teach the limitations or combined to being obvious to a person skilled in the art to
disclose the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABIGAIL MARIE THAYER whose telephone number is (571)270-0134. The examiner can normally be reached M-Th/F 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ABIGAIL MARIE THAYER/Examiner, Art Unit 2847
/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2847
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