Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pg. 7, filed 6/3/2026 with respect to the 112a and 112b rejections have been fully considered and are persuasive. The 112a and 112b rejections of claims 1-20 has been withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21, lines 1-2 recites “a field, of the plurality of fields, is spread across multiple groups of the plurality of groups”. Examiner finds the term “spread across” to be unclear and inconsistent with terminology in the rest of the application. For example, “spread across” in this context could mean that the entire field is included in multiple groups, or that some of the bits of the field are included in multiple groups. Examiner assumes in this action that the latter is the intended meaning, but recommends amending the claim consistent with the language of claim 1, for example “wherein bits of a field, of the plurality of fields, are included in multiple groups of the plurality of groups…” or “all bits of a field, of the plurality of fields, are included in each group of multiple groups of the plurality of groups…”
Further it is unclear whether the “a field” mentioned in claim 21 could be the “a first field” or the “a second field”- or if it is explicitly different than other fields. Examiner recommends amending the claim to make this clear. For example, “wherein a third field, of the plurality of fields…” or “wherein any one of the fields, of the plurality of fields…”.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-17 and 19-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8-14 of U.S. Patent No. 12093129 (herein Pawlowski) in view of. U.S. Patent No. 6738935 (herein Kimmitt).
Regarding claim 1 of the instant application, Pawlowski teaches:
A memory system, comprising: one or more processors; and one or more memories coupled with the one or more processors and comprising instructions which, when executed by the one or more processors, cause the memory system to: (claim 8: An apparatus, comprising: a processor; and a memory coupled with the processor and comprising instructions which, when executed by the processor, cause the apparatus to)
identify an access command for a memory device; generate a code word for the access command, the code word comprising a plurality of fields; (claim 8: identify an access command for a memory device; generate a code word for the access command, the code word comprising a plurality of fields;)
group bits of the code word into a plurality of groups, wherein bits of a first field of the plurality of fields are included in at least two of the plurality of groups (claim 1: group bits of the code word into a plurality of groups, wherein bits of a first field of the plurality of fields are included in at least two of the plurality of groups,)
and bits of one or more second fields of the plurality of fields are included in at least a group of the plurality of groups, (claim 8: the code word comprising a plurality of fields; group bits of the code word into a plurality of groups) Because the codeword comprises a plurality of fields, and the codeword is grouped, one of ordinary skill in the art would obviously recognize that there must be at least a second field part of the codeword that is included in at least a group.
and wherein each group of bits corresponds to one of a plurality of arrangements of fields, the plurality of arrangements of fields comprising a first arrangement of fields (claim 1: and wherein each group of bits corresponds to one of a plurality of arrangements of fields, the plurality of arrangements of fields comprising a first arrangement of fields)
… and transfer, to the memory device for the access command, the plurality of groups over a plurality of channels in a plurality of bursts according to the plurality of arrangements of fields, (claim 8: and transfer, to the memory device for the access command, the plurality of groups over a plurality of channels in a plurality of bursts according to the plurality of arrangements of fields.)
wherein each channel of the plurality of channels is associated with communicating a respective set of groups of the plurality of groups, and wherein each group of the respective set of groups for a channel is transferred in a respective burst of the plurality of bursts. (claim 8: wherein a respective set of groups of the plurality of groups is transferred over each channel of the plurality of channels, and wherein each group of the respective set of groups for a channel is transferred in a respective burst of the plurality of bursts.)
However, Pawlowski does not explicitly teach:
[one of the arrangements of fields] associated with the at least the group and comprising a set of error control bits associated with an error control operation for the bits of the first field;
In the analogous art of data transmission, Kimmitt teaches:
[one of the arrangements of fields] associated with the at least the group and comprising a set of error control bits associated with an error control operation for the bits of the first field; (col. 10, lines 46-53: The transmit data bus, monitor bit and ECC bits are divided into separate groups which are then scrambled as subsequently described and transmitted over respective channels. In the present embodiment, the 64 data bits comprising the parallel input data word, the monitor bit and the seven (7) ECC bits comprise 72 bits that are split into four 18 bit groups as indicated below. This is the function of the transmit interleaver 53.) Also see that in the 4 groups indicated below, each group includes at least one of 7 ECC bits. (Also see col. 9, lines 6-10: Shown below are the reduced XOR logical equations that constitute CRC function within the data ECC generator 52.) See that in the equations below, the ECC (CRC) bits are associated with the bits in the transmit data bus (effectively bits of a first field). It is well known in the art that CRC bits are used for an error control operation for the bits they are generated from. It would have been obvious to one of ordinary skill in the art, having the teachings of Pawlowski and Kimmitt before them to incorporate the ECC bits as a field when creating groups for a transmission over multiple channels (Kimmitt), into the system for grouping and transmitting fields (Pawlowski), to allow for benefits such as single bit error correction, double bit error detection and six bit burst error detection (Kimmitt, col. 8, lines 30-40).
Regarding claim 2, Pawlowski and Kimmitt teach the memory system of claim 1. Kimmitt further teaches wherein:
The error control operation comprises identification of one or more erroneous bits of the bits of the first field, correction of one or more erroneous bits, or both. (see col. 8, lines 30-40: The Data ECC generator 52 generates seven redundant bits, E<6:0>, from the 65-bit data payload comprising the data carried on TXD<63:0>; received from the XGMII Transmit Control Logic 50 and the monitor channel bit of the monitor channel 26. The seven ECC bits are generated using a CRC algorithm that provides single bit error correction, double bit error detection and six bit burst error detection.) The first field is considered to be equivalent to the 65-bit data payload.
It would have been obvious to one of ordinary skill in the art, having the teachings of Pawlowski and Kimmitt before them to incorporate the ECC bits as a field when creating groups for a transmission over multiple channels (Kimmitt), into the system for grouping and transmitting fields (Pawlowski), to allow for benefits such as single bit error correction, double bit error detection and six bit burst error detection (Kimmitt, col. 8, lines 30-40).
Regarding claim 3, Pawlowski and Kimmitt teach the memory system of claim 2. Kimmitt further teaches wherein:
The set of error control bits comprise a set of cyclic redundancy check (CRC) bits for identifying the one or more erroneous bits of the first field. (see col. 8, lines 30-40: The Data ECC generator 52 generates seven redundant bits, E<6:0>, from the 65-bit data payload comprising the data carried on TXD<63:0>; received from the XGMII Transmit Control Logic 50 and the monitor channel bit of the monitor channel 26. The seven ECC bits are generated using a CRC algorithm that provides single bit error correction, double bit error detection and six bit burst error detection.) The first field is considered to be equivalent to the 65-bit data payload.
It would have been obvious to one of ordinary skill in the art, having the teachings of Pawlowski and Kimmitt before them to incorporate the ECC bits as a field when creating groups for a transmission over multiple channels (Kimmitt), into the system for grouping and transmitting fields (Pawlowski), to allow for benefits such as single bit error correction, double bit error detection and six bit burst error detection (Kimmitt, col. 8, lines 30-40).
Regarding claim 4, Pawlowski and Kimmitt teach the memory system of claim 2. Kimmitt further teaches wherein:
The set of error control bits comprise a set of bits for performing an exclusive OR (XOR) operation with the one or more erroneous bits of the first field. (see col. 8, lines 30-40: The Data ECC generator 52 generates seven redundant bits E<6:0>, from the 65-bit data payload comprising the data carried on TXD<63:0>; received from the XGMII Transmit Control Logic 50 and the monitor channel bit of the monitor channel 26. The seven ECC bits are generated using a CRC algorithm that provides single bit error correction, double bit error detection and six bit burst error detection. Also see col. 9, lines 6-10: Shown below are the reduced XOR logical equations that constitute CRC function within the data ECC generator 52.) It is well known that error correction and detection operations using CRC ECC bits involve XOR operations.
Regarding claim 5, the combination of Pawlowski and Kimmitt teaches the memory system of claim 1. Pawlowski further teaches:
wherein a second arrangement of fields of the plurality of arrangements of fields comprises one or more control fields and one or more spare fields. (see claim 8: the first arrangement of fields comprises a first subset of bits of the first field and at least a subset of bits of a second field and the second arrangement of fields comprises a second subset of bits of the first field and at least a subset of bits of a third field. And see claim 9: wherein the first arrangement of fields comprises one or more control fields and one or more spare fields.) The first arrangement of fields in the cited art can be mapped to the second arrangement of fields in the instant application, and vice-versa.
Regarding claim 6, the combination of Pawlowski and Kimmitt teaches the memory system of claim 1. Pawlowski further teaches:
wherein at least two of the plurality of groups have a same arrangement of fields of the plurality of arrangements of fields. (see claim 10: wherein at least two of the plurality of groups have a same arrangement of fields of the plurality of arrangements of fields.)
Regarding claim 7, the combination of Pawlowski and Kimmitt teaches the memory system of claim 1. Pawlowski further teaches:
wherein the plurality of fields comprises a plurality of control fields and one or more data fields. (see claim 11: wherein the plurality of fields comprises a plurality of control fields and one or more data fields.)
Regarding claim 8, the combination of Pawlowski and Kimmitt teaches the memory system of claim 7. Pawlowski further teaches:
wherein the instructions for transferring the plurality of groups comprises instructions which, when executed by the one or more processors, cause the memory system to transfer the plurality of control fields in a first burst of the plurality of bursts. (see claim 12: wherein the instructions for transferring the plurality of groups comprises instructions which, when executed by the processor, cause the apparatus to transfer the plurality of control fields in a first burst of the plurality of bursts.)
Regarding claim 9, the combination of Pawlowski and Kimmitt teaches the memory system of claim 1. Pawlowski further teaches:
wherein each of the plurality of groups comprises eight bits. (see claim 13: wherein each of the plurality of groups comprises eight bits.)
Regarding claim 10, the combination of Pawlowski and Kimmitt teaches the memory system of claim 1. Pawlowski further teaches:
wherein each of the plurality of groups comprises a determined quantity of the bits. (see claim 14: wherein each of the plurality of groups comprises a determined quantity of the bits.)
Regarding claim 21, the combination of Pawlowski and Kimmitt teaches the memory system of claim 1. Kimmitt further teaches:
wherein a field, of the plurality of fields, is spread across multiple groups of the plurality of groups, and wherein the multiple groups are transferred on multiple channels of the plurality of channels. (see col. 10, lines 46-53: The transmit data bus, monitor bit and ECC bits are divided into separate groups which are then scrambled as subsequently described and transmitted over respective channels. In the present embodiment, the 64 data bits comprising the parallel input data word, the monitor bit and the seven (7) ECC bits comprise 72 bits that are split into four 18 bit groups as indicated below. This is the function of the transmit interleaver 53.) Also see that in the 4 groups (TXPa<17:0>, TXPb<17:0>, TXPc<17:0>, TXPd<17:0>) indicated below, each group includes at least one of 7 ECC bits. The ECC bits collectively are considered to constitute a field. Note that a subset of the ECC bit field is spread across multiple groups, those groups transferred on multiple channels.
It would have been obvious to one of ordinary skill in the art, having the teachings of Pawlowski and Kimmitt before them to incorporate the ECC bits as a field when creating groups for a transmission over multiple channels (Kimmitt), into the system for grouping and transmitting fields (Pawlowski), to allow for benefits such as single bit error correction, double bit error detection and six bit burst error detection (Kimmitt, col. 8, lines 30-40).
Claims 11-17, 19, and 20 correspond to claims 1-7, 10, and 1 (respectively), and are rejected accordingly.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK K BARNETT whose telephone number is (571)270-0431. The examiner can normally be reached M-Th 8-5, F 8-4 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at 571-270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACK KENSINGTON BARNETT/ Examiner, Art Unit 2111
/MARK D FEATHERSTONE/ Supervisory Patent Examiner, Art Unit 2111
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