Prosecution Insights
Last updated: October 27, 2026
Application No. 18/801,237

SEMICONDUCTOR MEMORY DEVICE INCLUDING A SUBSTRATE, VARIOUS INTERCONNECTIONS, SEMICONDUCTOR MEMBER, CHARGE STORAGE MEMBER AND A CONDUCTIVE MEMBER

Non-Final OA §102
Filed
Aug 12, 2024
Priority
Mar 10, 2016 — JP 2016-047644 +5 more
Examiner
LEE, KYOUNG
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
KIOXIA Corporation
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
941 granted / 1010 resolved
+25.2% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
11 currently pending
Career history
1029
Total Applications
across all art units

Statute-Specific Performance

§101
2.9%
-37.1% vs TC avg
§103
35.0%
-5.0% vs TC avg
§102
41.2%
+1.2% vs TC avg
§112
11.2%
-28.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1010 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 8/12/2024 was is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by SHIN et al. (US Patent Appl. Pub. No. 2015/0129878 A1). [Re claim 1] SHIN discloses the semiconductor memory device, comprising: a substrate (110); an integrated circuit (120, 130, 150) provided above the substrate, the integrated circuit including a first interconnect (158); a stacked body provided above the integrated circuit, the stacked body including electrode films (192, 194, 196, 198), semiconductor pillars (202), and memory films (204a, 204b, 204c) (see figure 8); a through-via (232) piercing the stacked body and connected to the first interconnect (158); and a second interconnect (236) provided above the stacked body and connected to the through-via (see figure 1B and paragraph [0044]-[0072]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYOUNG LEE whose telephone number is (571)272-1982. The examiner can normally be reached M to F, 10am to 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KYOUNG LEE/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Aug 12, 2024
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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METHOD FOR FABRICATING VERTICAL CHANNEL NANOWIRE TRANSISTOR WITH ASYMMETRIC STRESS DISTRIBUTION
3y 2m to grant Granted Oct 20, 2026
Patent 12772690
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2y 5m to grant Granted Oct 20, 2026
Patent 12772524
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2y 5m to grant Granted Oct 20, 2026
Patent 12765227
DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
3y 2m to grant Granted Oct 13, 2026
Patent 12765170
DISPLAY DEVICE
3y 1m to grant Granted Oct 13, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
98%
With Interview (+5.1%)
1y 11m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1010 resolved cases by this examiner. Grant probability derived from career allowance rate.

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