Prosecution Insights
Last updated: April 19, 2026
Application No. 18/801,299

ATTENUATOR FOR QUBIT DRIVE SIGNALS

Non-Final OA §103
Filed
Aug 12, 2024
Examiner
POOS, JOHN W
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Google LLC
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
2y 0m
To Grant
98%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allow Rate
1277 granted / 1365 resolved
+25.6% vs TC avg
Minimal +4% lift
Without
With
+4.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
36 currently pending
Career history
1401
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
29.4%
-10.6% vs TC avg
§102
58.1%
+18.1% vs TC avg
§112
6.3%
-33.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1365 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1, 3, and 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abdo (US 9,589,236), in view of Ohashi et al. (US 2015/0263406). In regard to Claim 1: Abdo discloses, in Figure 4A, a quantum computing apparatus comprising: one or more frequency sources (470); a dilution refrigerator (491); a quantum processor (405); a directional coupler (488); and a filter (493), wherein the quantum processor (405), the directional coupler (488), and the filter (493) are disposed within or in thermal equilibrium with a mixing chamber of the dilution refrigerator (491, Column 14: lines 51-62), and wherein the one or more frequency sources (470) are connected to the quantum processor (405) via the apparatus (498), but does not disclose an absorptive low pass filter. Ohashi discloses, in Figure 12, an absorptive low pass filter (30). It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the low pass filter taught by Ohashi with the filter taught by Abdo, in order to allow for suppression of changes in the power of the coupling signal or changes in the coupling of the directional coupler 1 with increases in the frequency of the high frequency signal (Ohashi Paragraph 0054). In regard to Claim 3: Abdo further discloses, in Figure 4A, the quantum computing apparatus of claim 1, wherein the directional coupler comprises a stripline directional coupler (Column 12: lines 26-29). In regard to Claim 10: Abdo further discloses, in Figure 4A, the quantum computing apparatus of claim 1, comprising: an enclosure (491, enclosure of the dilution refrigerator), wherein the directional coupler (488) and the absorptive low pass filter (493) are embedded in the enclosure (Column 13: lines 17-25); and a first connector and a second connector connected to a first port and a third port of the directional coupler (488), respectively, for connecting to a printed circuit board (PCB) (Column 13: lines 9-16). In regard to Claim 11: All of the claim limitations have been discussed with respect to Claims 1 and 10 above, except for wherein the enclosure has a thermal conductivity larger than 10-5 W/m/K. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to have an enclosure has a thermal conductivity larger than 10-5 W/m/K, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Further it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to have an enclosure has a thermal conductivity larger than 10-5 W/m/K, in order to allow for a continuous refrigeration method to reach temperatures below 0.3 K (Abdo Column 13: lines 17-25). Allowable Subject Matter Claims 2, 4-9 and 12-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ashida et al. (US 2017/0040661) discloses a directional coupler includes: a first to a fourth port; a main line connecting the first and second ports; a first to a fourth subline section electromagnetically coupled to the main line; a first to a third matching section; and a stack. The first subline, first matching, third subline, third matching, fourth subline, second matching, and second subline sections are arranged in this order between the third and fourth port. The first and second matching sections include an inductor connecting two subline sections located on opposite sides of the matching section. Each of one or more conductor layers used to form the inductor includes two connection portions for electrical connection to respective other elements, and a line portion connecting the two connection portions. The inductor excluding the connection portions does not include portions that overlap each other when viewed in the stacking direction of the stack. Uzawa et al. (US 2019/0097117) discloses Aa low-noise wide band amplifier is realized utilizing a superconductor-insulator-superconductor (SIS) junction, quasiparticle frequency mixers connected in tandem or in cascade, a first quasiparticle mixer performs first frequency mixing with use of a first local signal having a frequency not less than twice a frequency of an input signal to the first quasiparticle mixer, a second quasiparticle mixer performs second frequency mixing with use of a second local signal having a frequency not more than twice a frequency of an input signal to the second quasiparticle mixer, and signal amplification is performed through frequency conversion by extracting, from among a plurality of signals generated with the first and the second frequency mixing, a signal in a frequency band not more than a frequency band of the signal before the first frequency mixing and the second frequency mixing, using a transmission line or a filter. Abdo (US 10,164,724) discloses a superconducting microwave combiner. A first filter through a last filter connects to a first input through a last input, respectively. The first filter through the last filter each has a first passband through a last passband, respectively, such that the first passband through the last passband are each different. A common output is connected to the first input through the last input via the first filter through the last filter. Abdo et al. (US 9,735,776) discloses qubit drive and readout. A first lossless microwave switch is connected to a quantum system. A second lossless microwave switch is connectable to the first lossless microwave switch. A quantum-limited amplifier is connectable to the second lossless microwave switch. Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOHN W POOS/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Aug 12, 2024
Application Filed
Feb 27, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
98%
With Interview (+4.4%)
2y 0m
Median Time to Grant
Low
PTA Risk
Based on 1365 resolved cases by this examiner. Grant probability derived from career allow rate.

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