Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I in the reply filed on 3/30/26 is acknowledged.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claimed scope includes signal media, i.e. the claimed computer readable medium is not defined as non-transitory, and Applicant’s disclosure, e.g. paragraph 118, indicates that computer readable media includes communication media such as a signal or carrier wave.
Applicant is advised to amend the claim to recite “non-transitory” media in order to overcome this rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 13-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “EmerGPU: Understanding and Mitigating Resonance-Induced Voltage Noise in GPU Architectures” by Renji Thomas, et al. (hereinafter Thomas).
Regarding claim 1, the limitations “An apparatus for graphics processing, comprising: at least one memory; and at least one processor coupled to the at least one memory and, based at least in part on information stored in the at least one memory, the at least one processor individually or in combination, is configured to: obtain an indication of a set of graphics instructions; determine whether each graphics instruction in the set of graphics instruction is associated with a resonance frequency that is above or below a threshold” are taught by Thomas (Thomas, e.g. abstract, sections I-VII, describes EmerGPU, a solution which detects and mitigates resonance noise in GPUs. It is noted that Thomas’ describes this solution using language and figures that are similar to Applicant’s description and figures of the invention, i.e. Thomas, section IV, figures 9-12 corresponds to Applicant’s paragraphs 77, 79, 82-87, figures 8-11. Thomas, e.g. sections IV, IV A, IV B 1-2, figure 12, describes the resonance monitor hardware unit operating within the issue stage of a GPU streaming multiprocessor (SM) unit, which analyzes sequences of instructions received for execution by classifying each active warp as high or low power based in part on the instruction associated with the warp, and by extension each execution cycle is marked as high-activity or low-activity based on the warp classification. Thomas, e.g. section IV B 1, further teaches that the resource monitor tracks when the execution transitions from a low-activity cycle to a high-activity cycle, causing a period counter to start, and if the next low-to-high transition occurs within a number of cycles that is lower than the resonance period of the chip, the resonance monitor enters a resource mitigation mode for as long as the oscillation period is within the resonance region, where the resonance region corresponds to a set of thresholds defining the resonance frequency of the chip as shown in figure 9, i.e. the resonance frequency of the chip is a region rather than a literal single frequency, indicating the region is defined by a high and low threshold resonance frequency. That is, as claimed, Thomas’ resonance monitor receives/obtains indications of a set of graphics instructions, i.e. the active warps and their associated instructions, and determines whether each instruction/warp is associated with a resonance frequency that is above or below a threshold by monitoring execution transitions from low to high activity phases based on an execution cycle for a low power warp being followed by an execution cycle for a high power warp and activating the resonance mitigation mode for as long as the oscillation period is within the resonance region. It is additionally noted that Thomas, e.g. section V, teaches simulating EmerGPU using a computer, i.e. the system includes a memory storing instructions and a processor performing the claimed method for graphics processing applications such as the examples of Table III.)
The limitation “adjust an activity level for each graphics instruction in the set of graphics instructions based on the resonance frequency being above or below the threshold” is taught by Thomas (Thomas, e.g. section IV B 1-4, teaches that when the resonance monitor enters the resonance mitigation mode the monitor chooses either a high-frequency or low-frequency mitigation depending on the duty cycle, and disrupts the resonant activity by raising the warp injection flag/signal in different ways depending on which of the high-frequency or low-frequency modes are selected. Thomas’ resonance-aware warp selector unit, e.g. section IV B 3, is responsible for adjusting activity for the graphics instructions when the warp injection flag is set, first looking for a candidate warp/instruction in the sub-list of high-power warps, then for low-power warps which may be set with a power boost flag if a high-power warp is not found, and dispatching dummy warps when no low-power warp is found. Thomas’ resonance-aware warp execution stage, e.g. section IV B 3-4, further implements the adjusted activity for the warps/instructions being executed while the resonance mitigation mode is activated by examining the flags for a warp/instruction being executed, activating masked off lanes if the power boost flag is set, and disabling clock gating for dummy warps and warps with the power boost flag set, i.e. increasing activity for selected cycles in order to cause the oscillation frequency to be lower or higher than the bounds of the resonance region, corresponding to the claimed adjusting activity level operation.)
Regarding claims 2-4, the limitations “output, based on the determination, an indication to adjust the activity level of each graphics instruction in the set of graphics instructions based on the resonance frequency being above or below the threshold”, “transmit an identifier (ID) for each graphics instruction in the set of graphics instructions based on the resonance frequency being above or below the threshold”, and “transmit a warp injection flag that indicates to adjust the activity level of each graphics instruction in the set of graphics instructions based on the resonance frequency being above or below the threshold” are taught by Thomas (As discussed in the claim 1 rejection above, Thomas, e.g. section IV B 1-4, teaches that when the resonance monitor enters the resonance mitigation mode the monitor chooses either a high-frequency or low-frequency mitigation depending on the duty cycle, and disrupts the resonant activity by raising the warp injection flag/signal in different ways depending on which of the high-frequency or low-frequency modes are selected. That is, as claimed, based on the determination that the graphics instruction(s) are associated with an oscillation period in the resonance region, a warp injection flag is output as part of the indication to adjust the activity level of the graphics instruction(s), corresponding to the limitations in claims 2 and 4. Further, Thomas, section IV B 2, indicates that when the resonance mitigation mode is active, the warp power classifier classifies each warp as high or low power in an N-bit vector wherein element k indicates if the kth warp is high or low power, i.e. in addition to the warp injection flag, an identifier for each instruction/warp is transmitted/stored in the N-bit vector, corresponding to the identifier for each graphics instruction as in claim 3.)
Regarding claim 5, the limitation “output an indication of a set of dummy warps to indicate the adjustment of the activity level of each graphics instruction in the set of graphics instructions” is taught by Thomas (As discussed in the claim 1 rejection above, Thomas’ resonance-aware warp selector unit, e.g. section IV B 3, is responsible for adjusting activity for the graphics instructions when the warp injection flag is set, first looking for a candidate warp/instruction in the sub-list of high-power warps, then for low-power warps which may be set with a power boost flag if a high-power warp is not found, and dispatching dummy warps when no low-power warp is found, where the dummy warp causes a high power consumption without performing any actual execution.)
Regarding claim 13, the limitation “monitor, during a resonance period, for the indication of the set of graphics instructions prior to obtaining the indication of the set graphics instructions” is taught by Thomas (Thomas, e.g. section IV B 1, teaches that the resonance monitor continuously examines incoming instructions to look for oscillation periods close to the resonance region, i.e. the monitoring of the indication of the graphics instructions is performed continuously and therefore also monitored prior to obtaining at least some of the indications of the sets of graphics instructions.)
Regarding claim 14, the limitation “obtain the indication of the set of graphics instructions for an arithmetic logic unit (ALU) at a graphics processing unit (GPU) or a central processing unit (CPU)” is taught by Thomas (Thomas’ warps are associated with graphics instructions, including compute instructions executed by ALUs of the SMs of the GPU, e.g. section II A, section IV B 2.)
Regarding claim 15, the limitation “wherein each graphics instruction of the set of graphics instructions is further associated with a graphics processing activity that is above or below a power consumption threshold” is taught by Thomas (Thomas, section IV B 2, indicates that when the resonance mitigation mode is active, the warp power classifier classifies each warp as high or low power depending on the type of operation being performed and the number of active lanes relative to a threshold number of lanes. That is, the power consumption of executing a warp using a compute instruction is directly related to the number of active lanes, such that the threshold number of lanes corresponds to the claimed power consumption threshold, i.e. warps/instructions executing a memory type instruction or a compute type instruction with less than or equal to the threshold number of lanes is below the power consumption threshold are classified as low power, and warps/instruction executing a compute type instruction with more than the threshold number of active lanes is above the power consumption threshold are classified as high power.)
Regarding claim 16, the limitation “determine whether each graphics instruction in the set of graphics instructions is associated with a warp injection mode” is taught by Thomas (As discussed in the claim 1 rejection above, Thomas, e.g. section IV B 1-4, teaches that when the resonance monitor enters the resonance mitigation mode the monitor chooses either a high-frequency or low-frequency mitigation depending on the duty cycle, and disrupts the resonant activity by raising the warp injection flag/signal in different ways depending on which of the high-frequency or low-frequency modes are selected. Further, Thomas, section IV B 3, indicates that the warp injection flag is attached to all warps dispatched when a warp injection mode is active. That is, each graphics instruction/active warp in the SM at the time when the resonance mitigation mode is entered/activated may be determined to be associated with either a high-frequency warp injection mode or low-frequency warp injection mode, corresponding to the claimed determination of whether the instructions are associated with a resonance frequency includes determining whether the graphics instructions are associated with a warp injection mode.)
Regarding claims 17 and 18, the limitations “output an indication of the adjustment of the activity level of each graphics instruction in the set of graphics instructions”, “transmit the indication of the adjustment of the activity level of each graphics instruction in the set of graphics instructions; or store the indication of the adjustment of the activity level of each graphics instruction in the set of graphics instructions” are taught by Thomas (As discussed in the claim 1 rejection above, Thomas’ resonance-aware warp selector unit, e.g. section IV B 3, is responsible for adjusting activity for the graphics instructions when the warp injection flag is set, first looking for a candidate warp/instruction in the sub-list of high-power warps, then for low-power warps which may be set with a power boost flag if a high-power warp is not found, and dispatching dummy warps when no low-power warp is found. Thomas’ resonance-aware warp execution stage, e.g. section IV B 3-4, further implements the adjusted activity for the warps/instructions being executed while the resonance mitigation mode is activated by examining the flags for a warp/instruction being executed, activating masked off lanes if the power boost flag is set, and disabling clock gating for dummy warps and warps with the power boost flag set. That is, the claimed indication of the adjustment of the activity level of each graphics instruction corresponds to the flags attached to each instruction/warp, the power boost and warp injection flags, used to signal to the resonance-aware warp execution unit to disable clock gating and/or activate additional processing lanes, where said flags are both transmitted and stored, i.e. as in section IV B 3-4, figure 12, the flags are attached to the warps by the modified issue unit of the SM which are then stored in a register block prior to execution by the SIMD ALU. That is, as in claim 17, the flags/indication of the adjustment activity level of each instruction are output by the issue unit, and as in claim 18, the flags/indication are transmitted from the issue unit to the register block to the SIMD ALU, where a register block is a temporary storage unit, meaning the flags/indication are also stored.)
Regarding claims 19 and 20, the limitations are similar to those treated in the above rejection(s) and are met by the references as discussed in claim 1 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT BADER whose telephone number is (571)270-3335. The examiner can normally be reached 11-7 m-f.
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/ROBERT BADER/Primary Examiner, Art Unit 2611
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