DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to Application filed on 08/13/2024
Application claims a FP date of 08/18/2023
Claims 1, 10 and 17 are independent
Claims 1-20 are pending
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). It is noted, however, that applicant has not filed a certified copy of the priority document in the application as required by 37 CFR 1.55. An attempt by Office to electronically retrieve the foreign application 10-2023-0108391 to which priority is claimed has FAILED on 01/18/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/13/2024 is in compliance with the provisions of 37 CFR 1.97 and 37 CFR 1.98(a)(4). Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “variable switch” must be shown or the features canceled from the claims 6-7. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
Claims 6-7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims recite “variable switch” that has not been defined or described in the instant specification or Drawings.
Claim 6-7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claims contain subject matter as they recite “variable switch” which is not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 10-11 and 17-20 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Jeong et al. (U.S. Patent Publication Number 2023/0171519 A1).
Regarding Claim 1, Jeong discloses an image sensing device (Figs 1 and 2 discloses examples of an image sensor and Fig 3 shows the operation timing of an image sensor) comprising:
a latch array (Figs 1, 2- data buffer 150; In ¶0023, Jeong discloses that the data buffer 150 may store the pixel values transferred from the ADC circuitry 140 and may output the stored pixel values in response to an enable signal received from the timing controller 110; further in ¶0026, he discloses that the data buffer 150 may include plurality of memories 151 and the memory may be implemented with, for example, a latch; further in ¶0027, he discloses that each memory 151 may store a plurality of bits corresponding to the pixel value transferred from a corresponding ADC) including: a first latch group stores therein first image data corresponding to a first region of a pixel array (Figs 2 and 4 discloses the buffer group 151 and 450; In ¶0033, Jeong discloses that the data buffer 450 may be clustered into plurality of clusters 4501, 4502 … 450n and each of the buffer clusters 4501, 4502 … 450n may include plurality of memories 4511, 4512 …. 451n);
a second latch group stores therein second image data corresponding to a second region of the pixel array (Figs 2 and 4 discloses the buffer group 151 and 450; In ¶0033, Jeong discloses that the data buffer 450 may be clustered into plurality of clusters 4501, 4502 … 450n and each of the buffer clusters 4501, 4502 … 450n may include plurality of memories 4511, 4512 …. 451n);
a first latch controller generates a first latch control signal to control the first latch group (In Fig 4 and in ¶0034-¶0041, Jeong discloses that the timing controller 410 may transfer read enable signals EN1 to Enn to the data buffer clusters 4501 to 450n respectively. He also discloses that in some embodiments the timing controller 410 may be connected to the data buffer clusters 4501 to 450n via busses 4111, 4112 … 411n respectively); and
a second latch controller generates a second latch control signal to control the second latch group (Since in ¶0034-¶0041 Jeong discloses that the timing controller 410 controls plurality of clusters, it is clear that he discloses a second latch controller that is controlled by a control signal),
wherein a second edge of the second latch control signal occurs after a first edge of the first latch control signal (In ¶0030 Jeong discloses that the signal may be delayed whenever it passes through the memories 151. This is also explained in ¶0040 where he discloses that each memory 451j of each data buffer cluster 450j may read and output with a delay. Also see ¶0047).
Regarding Claim 2, Jeong discloses wherein: the first region includes a first column of the pixel array and the second region includes a second column of the pixel array (In ¶0036, Jeong discloses that data buffer clusters 4501 to 450n may correspond to column lines consecutively arranged among the column lines CL1 to CLN of the pixel array 410).
Regarding Claim 3, Jeong discloses wherein: the first edge occurs when the first latch control signal transitions from a logic low level to a logic high level, and the second edge occurs when the second latch control signal transitions from a logic low level to a logic high level (In ¶0028-¶0029 Jeong discloses that the memory 151 may read and output the ith bit among the M bits between the start edge of the enable pulse EN[i] and he start edge of the enable pulse EN[i+1]).
Regarding Claim 4, Jeong discloses wherein a pulse width of the first latch control signal and a pulse width of the second latch control signal are different from each other (Fig 8 discloses this – since each signal has a delay between the lines, it is clear that the width of EN1[1] is different from ENn[0]).
Regarding Claim 5, Jeong discloses wherein the first latch controller and the second latch controller are activated by a same control start signal (Figs 2-4 – the timing controller 410 eventually controls all the latch controller; also see ¶0027-¶0028).
Regarding Claim 10, this claim has limitation similar to claim 1. Claim 10 is rejected on the same grounds as Claim 1.
Regarding Claim 11, this claim has limitation similar to claim 2. Claim 11 is rejected on the same grounds as Claim 2.
Regarding Claim 17, this claim is a methods claim has limitation similar to claim 1. Claim 17 is rejected on the same grounds as Claim 1.
Regarding Claim 18, Jeong discloses wherein the storing the first image data includes: receiving a first classification signal; and receiving a second classification signal (In ¶0007 and throughout, Jeong discloses that pixels values may be stored in response to enable signals. He discloses that the timing controller may output a first enable signal and a second enable signal. Examiner would like to state the “classification signal” has not been defined in the claim and examiner believes that Jeong “enable signal” is a reasonable interpretation of classification).
Regarding Claim 19, Jeong discloses wherein the storing the first image data further includes storing a first data group included in the first image data in response to the first classification signal (In ¶0007 and throughout, Jeong discloses that pixels values may be stored in response to enable signals. He discloses that the timing controller may output a first enable signal and a second enable signal. The first data buffer cluster may store the plurality of first pixel values and may out the plurality of first pixel values in response to the first enable signal. The second data buffer cluster may store the plurality of second pixel values and may output the plurality of second pixel values in response to the second enable signal. Examiner would like to state the “classification signal” has not been defined in the claim and examiner believes that Jeong “enable signal” is a reasonable interpretation of classification).
Regarding Claim 20, Jeong discloses wherein the storing the first image data further includes storing, after the storing the first data group, a second data group included in the first image data in response to the second classification signal (Jeong discloses this in ¶0027-¶0028 and he also discloses that the timing controller 110 may output the enable pulses EN[M-1: 0] so that after a predetermined time has elapsed from a start edge of an enable pulse EN[i], a next enable pulse EN[i+1] has a start edge).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 8, 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al. (U.S. Patent Publication Number 2023/0171519 A1) in view of Choi et al. (U. S. Patent Publication Number 2020/0387453 A1).
Regarding Claim 6, Jeong disclose wherein the first latch controller includes a plurality of signal delay cells each delays a start time of an input signal (Jeong discloses this in ¶0027-¶0028 and he also discloses that the timing controller 110 may output the enable pulses EN[M-1: 0] so that after a predetermined time has elapsed from a start edge of an enable pulse EN[i], a next enable pulse EN[i+1] has a start edge)
However, Jeong fails to clearly disclose wherein the first latch controller includes: a variable switch adjusts a time point of an edge of the first latch control signal such that different pixel groups included in the first region correspond to edges at different time points;
Instead in a similar endeavor, Choi discloses wherein the first latch controller (Fig 2 – control logic 125 includes a latch controller 128 and delay time controller 129) includes: a plurality of signal delay cells each delays a start time of an input signal (In ¶0055-¶0056 Choi teaches that the delay time controller 129 may control an evaluation delay time which may be a time from a point of time when the pre-charge of the bus is ended to a point of time when the transmission of data stored in any one of the cache latches is started through the bus); and
a variable switch adjusts a time point of an edge of the first latch control signal such that different pixel groups included in the first region correspond to edges at different time points (In ¶0057, Choi also teaches that the delay time controller 129 may control a pre-charge delay time PDELAY_TIME; In ¶0100 Choi also teaches that the bus voltage level at which the bus is pre-charged and/or a time for which the bus is pre-charged is different set for the respective page buffers).
Jeong and Choi are combinable because both are related to memory/storage devices.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the delay time controller as taught by Choi in the imaging module disclosed by Jeong.
The suggestion/motivation for doing so would have been so that “the time for which the bus is pre-charged is differently set for respective page buffers so that the reliability of data can be assured” as disclosed by Choi in ¶0100.
Therefore, it would have been obvious to combine Jeong and Choi to obtain the invention as specified in claim 6.
Regarding Claim 8, Jeong in view of Choi discloses wherein each of the plurality of data groups includes data pieces corresponding to the same analog-to-digital converter (ADC) (Jeong: Jeong discloses this in Fig 4 where the data groups correspond to the same ADC 440).
Regarding Claim 12, this claim has limitation similar to claim 6. Claim 12 is rejected on the same grounds as Claim 6.
Regarding Claim 13, Jeong in view of Choi discloses wherein the first latch group (Jeong: Figs 2 and 4 discloses the buffer group 151 and 450; In ¶0033, Jeong discloses that the data buffer 450 may be clustered into plurality of clusters 4501, 4502 … 450n and each of the buffer clusters 4501, 4502 … 450n may include plurality of memories 4511, 4512 …. 451n) is further configured to receive classification signals (Examiner would like to state the “classification signal” has not been defined in the claim and examiner believes that Jeong’s “enable signal” is a reasonable interpretation of classification) to adjust start time points of storing therein a plurality of data groups included in the first image data such that the first latch group stores therein the plurality of data groups at different time points (Jeong: In ¶0007 and throughout, Jeong discloses that pixels values may be stored in response to enable signals. He discloses that the timing controller may output a first enable signal and a second enable signal. The first data buffer cluster may store the plurality of first pixel values and may out the plurality of first pixel values in response to the first enable signal. The second data buffer cluster may store the plurality of second pixel values and may output the plurality of second pixel values in response to the second enable signal.).
Regarding Claim 14, Jeong in view of Choi discloses wherein the classification signals are for determination of the start time points of storing the plurality of data groups in the first latch group (Jeong: Jeong discloses this in ¶0027-¶0028 and he also discloses that the timing controller 110 may output the enable pulses EN[M-1: 0] so that after a predetermined time has elapsed from a start edge of an enable pulse EN[i], a next enable pulse EN[i+1] has a start edge).
Regarding Claim 15, Jeong in view of Choi discloses wherein each of the plurality of data groups includes data pieces corresponding to the same analog-to-digital converter (ADC) (Jeong: Jeong discloses this in Fig 4 where the data groups correspond to the same ADC 440).
Allowable Subject Matter
Claims 7, 9 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
REASONS FOR ALLOWANCE
The following is an examiner’s statement of reasons for allowance:
Regarding claim 7 the cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious an image sensing device as recited in “wherein the variable switch adjusts the time point of the edge of the first latch control signal by adjusting the number of signal delay cells corresponding to the first region in response to a classification signal” as combined with other limitations in claims 1 and 6.
Regarding claim 9 the cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious an image sensing device as recited in “wherein each of the plurality of pixel groups includes pixels corresponding to the same color” as combined with other limitations in claims 1 and 6.
Regarding claim 16 the cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious an image sensing device as recited in “wherein each of the plurality of pixel groups includes pixels corresponding to the same color” as combined with other limitations in claims 10, 12 and 13.
Reference Cited
The following prior art made of record but not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (U.S. Patent Number 11,488,560 B2) discloses a data integrated circuit including: a data driving circuit, a shift register configured to output a plurality of latch clock signals, a latch configured to latch a plurality of image signals in response to the plurality of latch clock signals and output a plurality of digital image signals in response to a plurality of latch output signals, and a clock generator configured to divide a main clock signal into the plurality of latch output signals and output the plurality of divided latch output signals to the latch. At least two of the latch output signals are activated at different time intervals.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PADMA HALIYUR whose telephone number is (571)272-3287. The examiner can normally be reached Monday-Friday 7AM - 4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Twyler Haskins can be reached at 571-272-7406. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PADMA HALIYUR/Primary Examiner, Art Unit 2639 December 31, 2025