DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Japan on August 22, 2023. It is noted, however, that applicant has not filed a certified copy of the JP2023-134779 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7-8, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US PG-Pub No.: 2021/0351287 A1, hereinafter, “Chen”).
Regarding claim 1, Chen discloses a nitride semiconductor device (see Chen, FIG. 1), comprising:
an electron transit layer (106, ¶ [0071]) composed of a first nitride semiconductor (GaN, ¶ [0071]);
an electron supply layer (108, ¶ [0071]) arranged on the electron transit layer (106) and composed of a second nitride semiconductor (AlN. ¶ [0071]) having a bandgap that is larger than that of the first nitride semiconductor (GaN);
a gate layer (110, ¶ [0071]) arranged on part of the electron supply layer (108) and composed of a third nitride semiconductor (¶ [0071]);
a gate electrode (118, ¶ [0061]) arranged on the gate layer (110); and
a source electrode (116, ¶ [0060]) and a drain electrode (120, ¶ [0060]) that are arranged on the electron supply layer (108), wherein
the gate layer (110) includes
a first gate portion (left 110),
a second gate portion (right 110), and
a recess between the first gate portion (left 110) and the second gate portion (right 110, FIG. 1),
the gate electrode (118) is arranged over both the first gate portion (left 110) and the second gate portion (right 110), and
the nitride semiconductor device further includes an insulator (114, ¶ [0060]) located in the recess (FIG. 1).
Regarding claim 2, Chen discloses the nitride semiconductor device according to claim 1, wherein the insulator (114) includes a filler filling the recess of the gate layer (110), and an upper projection formed integrally with the filler and projecting out of the recess (FIG. 1).
Regarding claim 3, Chen discloses the nitride semiconductor device according to claim 2, wherein the upper projection of the insulator (114) includes a first overlapping portion covering part of an upper surface of the first gate portion (left 110), and a second overlapping portion covering part of an upper surface of the second gate portion (right 110, FIG. 1).
Regarding claim 7, Chen discloses the nitride semiconductor device according to claim 1, wherein the electron supply layer (108) is at least partially exposed in the recess (FIG. 1), and the insulator (114) is in contact with the electron supply layer (108) in the recess (FIG. 1).
Regarding claim 8, Chen discloses the nitride semiconductor device according to claim 1, wherein the insulator (114) has a thickness that is less than that of each of the first gate portion (left 110) and the second gate portion (right 110), and part of the gate electrode (118) is embedded in the recess (FIG. 1).
Regarding claim 10, Chen disclose the nitride semiconductor device according to claim 1, wherein the insulator (114) is composed of one or any combination of SiO2, SiN, SiON, A1203,AIN, and AION (¶ [0063]).
Allowable Subject Matter
Claims 4-6, 9, and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record neither anticipates nor renders obvious all the claimed subject of base claim 4, in particular, the first overlapping portion extends in a first direction over a first extension length from a first opening edge of the recess corresponding to an upper inner edge of the first gate portion and covers the upper surface of the first gate portion, the second overlapping portion extends in a second direction that is opposite to the first direction (left) over a second extension length from a second opening edge of the recess corresponding to an upper inner edge of the second gate portion and covers the upper surface of the second gate portion, and the first extension length and the second extension length are each greater than or equal to 10 nm and less than or equal to 200 nm.
The prior art of record neither anticipates nor renders obvious all the claimed subject of base claim 5, in particular, the first overlapping portion and the second overlapping portion each have a thickness that is greater than or equal to 10 nm and less than or equal to 200 nm.
The prior art of record neither anticipates nor renders obvious all the claimed subject of base claim 6, in particular, the recess includes a bottom portion composed of the third nitride semiconductor, and the insulator is arranged on the bottom portion without contacting the electron supply layer.
The prior art of record neither anticipates nor renders obvious all the claimed subject of base claim 9, in particular, the source electrode includes a source contact contacting the electron supply layer, the drain electrode includes a drain contact contacting the electron supply layer, and the gate layer includes a source-side extension extending from the first gate portion toward the source contact, and a drain-side extension extending from the second gate portion toward the drain contact.
The prior art of record neither anticipates nor renders obvious all the claimed subject of base claim 11, in particular, the electron supply layer is an AIGaN layer, and the gate layer is a GaN layer including acceptor impurities of at least one of Mg and Zn.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIA L. CROSS whose telephone number is (571)270-3273. The examiner can normally be reached 9 am-5:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/XIA L CROSS/ Primary Examiner, Art Unit 2892
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