3DETAILED ACTION
This office action is responsive to application 18/802,062 filed on August 13, 2024. Claims 1 and 12-32 are pending in the application and have been examined by the Examiner.
Information Disclosure Statement
The Information Disclosure Statement (IDS) filed on August 14, 2024 was received and has been considered by the Examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 18/067,929, filed on December 19, 2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 19, 22, 27 and 31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sambonsugi (US 2020/0128200).
Consider claim 19, Sambonsugi teaches:
A photoelectric conversion apparatus comprising:
pixels (200) disposed two-dimensionally in a row direction and a column direction (see figures 2A and 2B, paragraph 0036);
an L number of (L is 3 or greater integer) vertical signal lines (column output lines, 300) disposed on each pixel column (e.g. 12 column output lines (300), as shown in figures 2A and 2B, paragraph 0041);
an M number of (M is 2 or greater integer) selection circuits (selection switches, 206) disposed in each pixel (e.g. 3 selection switches (206a, 206b, 206c) disposed in each pixel (200), as shown in figure 2B, paragraph 0039), each of the selection circuits (206) respectively connecting one of the pixels (200) to a different vertical signal line (300, i.e. via output terminals 207a, 207b and 207c, respectively, figures 2A and 2B, paragraph 0041);
a vertical scanning circuit (vertical scanning circuit, 303, figure 2A) configured to scan the selection circuits (206a, 206b, 206c, i.e. by supplying control signals sel0 to sel2, figure 2B, paragraph 0041); and
a control unit (CPU, 102, figure 1, paragraph 0084),
wherein the control unit (102) is configured to set first operation mode in which the vertical scanning circuit (303) performs a single read scanning operation at a time (For instance, in the mode corresponding to frame number “LV_0” in figure 7A, a single read scanning operation for scanning only VOB_0 is performed, paragraphs 0070 and 0071.), and a second operation mode in which the vertical scanning circuit (303) performs a plurality of read scanning operations at a time (For instance, in the mode corresponding to frame number “LV_3” in figure 7B, a plurality of read scanning operations at a time are performed including a first read scanning operation for scanning VOB_0 and a second read scanning operation for scanning VOB_1, paragraphs 0070 and 0071.),
wherein, in the first operation mode (i.e. for LV_0 in figure 7A), the control unit (102) is configured to perform the single read scanning operation using a first selection circuit (206b) out of the M number of selection circuits (i.e. such that a signal is output via output terminal 207b, see figures 7A and 2B), and
wherein, in the second operation mode (i.e. for LV_3 in figure 7B), the control unit (102) is configured to perform an operation which is one of the plurality of read scanning operations, using a second selection circuit (206c), which is different from the first selection circuit, out of the M number of selection circuits (For instance, during the scanning of VOB_0, a signal is output via output terminal 207c, see figures 7B and 2B.).
Consider claim 22, and as applied to claim 19 above, Sambonsugi further teaches that the plurality of read scanning operations in the second operation mode (i.e. for LV_3 in figure 7B) include a first read scanning operation and a second read scanning operation, and wherein a pixel row to be read in the first read scanning operation is different from that to be read in the second read scanning operation (Pixels 0_0 to 10_0 are read in a first read scanning operation, wherein pixels 12k+0_0 to 12k+10_0 are read in the second operation, as shown in figure 7B.).
Consider claim 27, Sambonsugi teaches:
A photoelectric conversion system comprising:
a photoelectric conversion apparatus (see figures 2A and 2B);
and a signal processing unit (image processing unit, 107) configured to process signals outputted from the photoelectric conversion apparatus (“The CPU 102 transfers the inputted LV image data to the image processing unit 107, develops the LV image data in a development circuit (not illustrated) in the image processing unit 107, and starts display as a live-view image on the display unit 104.” paragraph 0110),
wherein the photoelectric conversion apparatus comprises:
pixels (200) disposed two-dimensionally in a row direction and a column direction (see figures 2A and 2B, paragraph 0036);
an L number of (L is 3 or greater integer) vertical signal lines (column output lines, 300) disposed on each pixel column (e.g. 12 column output lines (300), as shown in figures 2A and 2B, paragraph 0041);
an M number of (M is 2 or greater integer) selection circuits (selection switches, 206) disposed in each pixel (e.g. 3 selection switches (206a, 206b, 206c) disposed in each pixel (200), as shown in figure 2B, paragraph 0039), each of the selection circuits (206) respectively connecting one of the pixels (200) to a different vertical signal line (300, i.e. via output terminals 207a, 207b and 207c, respectively, figures 2A and 2B, paragraph 0041);
a vertical scanning circuit (vertical scanning circuit, 303, figure 2A) configured to scan the selection circuits (206a, 206b, 206c, i.e. by supplying control signals sel0 to sel2, figure 2B, paragraph 0041); and
a control unit (CPU, 102, figure 1, paragraph 0084),
wherein the control unit (102) is configured to set first operation mode in which the vertical scanning circuit (303) performs a single read scanning operation at a time (For instance, in the mode corresponding to frame number “LV_0” in figure 7A, a single read scanning operation for scanning only VOB_0 is performed, paragraphs 0070 and 0071.), and a second operation mode in which the vertical scanning circuit (303) performs a plurality of read scanning operations at a time (For instance, in the mode corresponding to frame number “LV_3” in figure 7B, a plurality of read scanning operations at a time are performed including a first read scanning operation for scanning VOB_0 and a second read scanning operation for scanning VOB_1, paragraphs 0070 and 0071.),
wherein, in the first operation mode (i.e. for LV_0 in figure 7A), the control unit (102) is configured to perform the single read scanning operation using a first selection circuit (206b) out of the M number of selection circuits (i.e. such that a signal is output via output terminal 207b, see figures 7A and 2B), and
wherein, in the second operation mode (i.e. for LV_3 in figure 7B), the control unit (102) is configured to perform an operation which is one of the plurality of read scanning operations, using a second selection circuit (206c), which is different from the first selection circuit, out of the M number of selection circuits (For instance, during the scanning of VOB_0, a signal is output via output terminal 207c, see figures 7B and 2B.),
wherein the signal processing unit (107) generates a first image using the signals read out in the first operation mode, and generates a second image using the signals read out in the second operation mode (As detailed in paragraph 0110, the signal processing unit (107) develops the live view (LV) image data. As such the signal processing unit generates a first image based on frame LV_0 in figure 7A and a second image based on frame LV_3 of figure 7B, paragraphs 0107-0110 and 0126-0129.).
Consider claim 31, Sambonsugi teaches:
A photoelectric conversion system comprising:
the photoelectric conversion apparatus according to claim 19 (see claim 19 rationale); and
a signal processing unit (image processing unit, 107, figure 1) configured to process signals outputted from the photoelectric conversion apparatus (i.e. to perform correction processing, compression processing, and the like, paragraph 0034).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Sambonsugi (US 2020/0128200) in view of Ogino et al. (US 2019/0371836).
Consider claim 32, Sambonsugi teaches:
A body (image capturing apparatus, 1000, figure 1, paragraph 0030) comprising the photoelectric conversion apparatus according to claim 19 (see claim 19 rationale).
However, Sambonsugi does not explicitly teach that the body is a mobile body comprising a moving device; a processing device configured to acquire information from signals outputted from the photoelectric conversion apparatus; and a control device configured to control the moving device based on the information.
Ogino et al. similarly teaches a photoelectric conversion apparatus (500, figure 13A, paragraph 0102).
However Ogino et al. additionally teaches that the body is a mobile body (“moving body”, paragraph 0101, figures 13A and 13B) comprising a moving device (i.e. a vehicle, figure 13B, paragraphs 0102-0105), a processing device (image processing unit, 412, figure 13A) configured to acquire information from signals outputted from the photoelectric conversion apparatus (500, see figure 13A, paragraph 0102), and a control device (control ECU, 430, figures 13A and 13B) configured to control the moving device based on the information (e.g. to cause a braking force, see paragraphs 0102 and 0103).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the photoelectric conversion apparatus taught by Sambonsugi be incorporated into a moving body as taught by Ogino et al. for the benefit of enabling collision prevention (Ogino et al., paragraph 0103).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Sambonsugi (US 2020/0128200) in view of Hayashi et al. (US 10,567,747).
Consider claim 25, and as applied to claim 19 above, Sambonsugi does not explicitly teach that each of the pixels includes two photodiodes and a floating diffusion connected to the two photodiodes, and wherein the selection circuit is configured to connect the floating diffusion and the vertical signal line.
Hayashi et al. similarly teaches a pixel array (1, figure 1) having pixels (10, column 3, lines 24-36) each including multiple selection circuits (select transistors, 109, 110, figure 2, column 4, lines 18-21).
However, Hayashi et al. additionally teaches that each of the pixels (10, figure 2) includes two photodiodes (photoelectric conversion elements, 101, 102) and a floating diffusion (FD) connected to the two photodiodes (see figure 2, column 4, lines 18-46), and wherein the selection circuit (109, 110) is configured to connect the floating diffusion (FD) and the vertical signal lines (111, 112, see figure 2, column 5, lines 24-35).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have each of the pixels taught by Sambonsugi include two photodiodes as taught by Hayashi et al. for the benefit of enabling short circuit detection (Hayashi et al., column 23, lines 1-9).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Sambonsugi (US 2020/0128200) in view of Suzuki et al. (US 2023/0300488).
Consider claim 26, and as applied to claim 19 above, Sambonsugi does not explicitly teach a first substrate on which the pixels are disposed, and a second substrate on which a signal processing unit that processes signals read from the pixels is disposed, wherein the first substrate and the second substrate are stacked.
Suzuki similarly teaches an imaging device (figure 1) having an array of pixels (pixel circuit, 2, paragraph 0059).
However, Suzuki additionally teaches a first substrate (11, figure 2) on which the pixels (2) are disposed (see paragraph 0062), and a second substrate (12) on which a signal processing unit that processes signals read from the pixels is disposed (“On the second substrate 12 located below the X-ray shielding plate 16, a wiring layer 17 connected to the pixel circuit 2 and peripheral circuits 18 such as the DSF circuit 5, the S/H circuit 6, the ADC 7, and the IF circuit 9 which are illustrated in FIG. 1, and a wiring circuit are formed.” paragraph 0063), wherein the first substrate (11) and the second substrate (12) are stacked (see figure 2).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the photoelectric conversion apparatus taught by Sambonsugi include first and second substrates as taught by Suzuki for the benefit of providing an imaging device with low noise, high speed and a high dynamic range (Suzuki, paragraph 0009).
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Sambonsugi (US 2020/0128200) in view of Ashida et al. (US 2013/0258134).
Consider claim 28, Sambonsugi teaches:
A photoelectric conversion system comprising:
a photoelectric conversion apparatus (see figures 2A and 2B);
and a signal processing unit (image processing unit, 107) configured to process signals outputted from the photoelectric conversion apparatus (“The CPU 102 transfers the inputted LV image data to the image processing unit 107, develops the LV image data in a development circuit (not illustrated) in the image processing unit 107, and starts display as a live-view image on the display unit 104.” paragraph 0110),
wherein the photoelectric conversion apparatus comprises:
pixels (200) disposed two-dimensionally in a row direction and a column direction (see figures 2A and 2B, paragraph 0036);
an L number of (L is 3 or greater integer) vertical signal lines (column output lines, 300) disposed on each pixel column (e.g. 12 column output lines (300), as shown in figures 2A and 2B, paragraph 0041);
an M number of (M is 2 or greater integer) selection circuits (selection switches, 206) disposed in each pixel (e.g. 3 selection switches (206a, 206b, 206c) disposed in each pixel (200), as shown in figure 2B, paragraph 0039), each of the selection circuits (206) respectively connecting one of the pixels (200) to a different vertical signal line (300, i.e. via output terminals 207a, 207b and 207c, respectively, figures 2A and 2B, paragraph 0041);
a vertical scanning circuit (vertical scanning circuit, 303, figure 2A) configured to scan the selection circuits (206a, 206b, 206c, i.e. by supplying control signals sel0 to sel2, figure 2B, paragraph 0041); and
a control unit (CPU, 102, figure 1, paragraph 0084),
wherein the control unit (102) is configured to set first operation mode in which the vertical scanning circuit (303) performs a single read scanning operation at a time (For instance, in the mode corresponding to frame number “LV_0” in figure 7A, a single read scanning operation for scanning only VOB_0 is performed, paragraphs 0070 and 0071.), and a second operation mode in which the vertical scanning circuit (303) performs a plurality of read scanning operations at a time (For instance, in the mode corresponding to frame number “LV_3” in figure 7B, a plurality of read scanning operations at a time are performed including a first read scanning operation for scanning VOB_0 and a second read scanning operation for scanning VOB_1, paragraphs 0070 and 0071.),
wherein, in the first operation mode (i.e. for LV_0 in figure 7A), the control unit (102) is configured to perform the single read scanning operation using a first selection circuit (206b) out of the M number of selection circuits (i.e. such that a signal is output via output terminal 207b, see figures 7A and 2B), and
wherein, in the second operation mode (i.e. for LV_3 in figure 7B), the control unit (102) is configured to perform an operation which is one of the plurality of read scanning operations, using a second selection circuit (206c), which is different from the first selection circuit, out of the M number of selection circuits (For instance, during the scanning of VOB_0, a signal is output via output terminal 207c, see figures 7B and 2B.),
wherein the signal processing unit (107) generates a first image using the signals read out in the first operation mode, and generates a second image using the signals read out in the second operation mode (As detailed in paragraph 0110, the signal processing unit (107) develops the live view (LV) image data. As such the signal processing unit generates a first image based on frame LV_0 in figure 7A and a second image based on frame LV_3 of figure 7B, paragraphs 0107-0110 and 0126-0129.).
However, Sambonsugi does not explicitly teach that the signal processing unit detects whether flicker is present or not using the signals read out in the second operation mode.
Ashida et al. similarly teaches a photoelectric conversion system (figure 1) comprising a signal processing unit (calculation/processing unit, 50, paragraph 0041).
However, Ashida et al. additionally teaches that the signal processing unit detects whether flicker is present or not using live view image data (“flicker detection and LED detection may be performed in a live view image, which is to be captured continuously in time immediately before a shutter switch is pressed” paragraphs 0093 and 0041).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the signals read out in the second operation mode taught by Sambonsugi be used by the signal processing unit to detect whether flicker is present or not as taught by Ashida et al. for the benefit of enabling an accurate determination to be made about whether a subject including light from a flashing LED is being imaged (Ashida et al., paragraph 0012).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 19-26, 31 and 32 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 and 11 of U.S. Patent No. 12,088,933. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 19-26, 31 and 32 are anticipated by claims 1-8 and 11 of US 12,088,933 as follows:
Consider claim 19, claim 1 of US 12,088,933 teaches (in parentheses):
A photoelectric conversion apparatus comprising: (A photoelectric conversion apparatus comprising:)
pixels disposed two-dimensionally in a row direction and a column direction, and each including a photoelectric conversion element configured to receive an incident light; (pixels disposed two-dimensionally in a row direction and a column direction, and each including a photoelectric conversion element configured to receive an incident light;)
an L number of (L is 3 or greater integer) vertical signal lines disposed on each pixel column; (an L number of (L is 3 or greater integer) vertical signal lines disposed on each pixel column;)
an M number of (M is 2 or greater integer) selection circuits disposed in each pixel, each of the selection circuits respectively connecting one of the pixels to a different vertical signal line; (an M number of (M is 2 or greater integer) selection circuits disposed in each pixel, each of the selection circuits respectively connecting one of the pixels to a different vertical signal line;)
a vertical scanning circuit configured to scan the selection circuits; (a vertical scanning circuit configured to scan the selection circuits;) and
a control unit, (a control unit)
wherein the control unit is configured to set a first operation mode in which the vertical scanning circuit performs a single read scanning operation at a time, and a second operation mode in which the vertical scanning circuit performs a plurality of read scanning operations at a time, (the control unit is configured to set a first operation mode in which the vertical scanning circuit performs a single read scanning operation at a time, and a second operation mode in which the vertical scanning circuit performs a plurality of read scanning operations at a time)
wherein, in the first operation mode, the control unit is configured to perform the single read scanning operation using a first selection circuit out of the M number of selection circuits, (in the first operation mode, the control unit is configured to perform the read scanning operation using a first selection circuit out of the M number of selection circuits) and
wherein, in the second operation mode, the control unit is configured to perform an operation which is one of the plurality of read scanning operations, using a second selection circuit, which is different from the first selection circuit, out of the M number of selection circuits (and wherein, in the second operation mode, the control unit is configured to perform the read scanning operation using a second selection circuit, which is different from the first selection circuit, out of the M number of selection circuits).
Consider claim 20, claim 1 of US 12,088,933 teaches (in parentheses):
the plurality of read scanning operations in the second operation mode include a first read scanning operation and a second read scanning operation, and wherein a cycle of the first read scanning operation is longer than a cycle of the second read scanning operation (the plurality of read scanning operations in the second operation mode include a first read scanning operation and a second read scanning operation, and wherein a cycle of the first read scanning operation is longer than a cycle of the second read scanning operation).
Consider claim 22, claim 2 of US 12,088,933 teaches (in parentheses):
the plurality of read scanning operations in the second operation mode include a first read scanning operation and a second read scanning operation, and wherein a pixel row to be read in the first read scanning operation is different from that to be read in the second read scanning operation (the plurality of read scanning operations in the second operation mode include a first read scanning operation and a second read scanning operation, and wherein a pixel row to be read in the first read scanning operation is different from that to be read in the second read scanning operation).
Consider claim 23, claim 3 of US 12,088,933 teaches (in parentheses):
a number of pixel rows to be read in the first read scanning operation is larger than a number of pixel rows to be read in the second read scanning operation (a number of pixel rows to be read in the first read scanning operation is larger than a number of pixel rows to be read in the second read scanning operation).
Consider claim 25, claim 4 of US 12,088,933 teaches (in parentheses):
each of the pixels includes two photodiodes and a floating diffusion connected to the two photodiodes, and wherein the selection circuit is configured to connect the floating diffusion and the vertical signal line (each of the pixels includes two photodiodes and a floating diffusion connected to the two photodiodes, and wherein the selection circuit is configured to connect the floating diffusion and the vertical signal line).
Consider claim 26, claim 5 of US 12,088,933 teaches (in parentheses):
a first substrate on which the pixels are disposed, and a second substrate on which a signal processing unit that processes signals read from the pixels is disposed, wherein the first substrate and the second substrate are stacked (a first substrate on which the pixels are disposed, and a second substrate on which a signal processing unit that processes signals read from the pixels is disposed, wherein the first substrate and the second substrate are stacked).
Consider claim 31, claim 6 of US 12,088,933 teaches (in parentheses):
A photoelectric conversion system comprising: the photoelectric conversion apparatus according to claim 19; and a signal processing unit configured to process signals outputted from the photoelectric conversion apparatus (A photoelectric conversion system comprising: the photoelectric conversion apparatus according to claim 1; and a signal processing unit configured to process signals outputted from the photoelectric conversion apparatus).
Consider claim 32, claim 7 of US 12,088,933 teaches (in parentheses):
A mobile body comprising: the photoelectric conversion apparatus according to claim 19; a moving device; a processing device configured to acquire information from signals outputted from the photoelectric conversion apparatus; and a control device configured to control the moving device based on the information (A mobile body comprising: the photoelectric conversion apparatus according to claim 1; a moving device; a processing device configured to acquire information from signals outputted from the photoelectric conversion apparatus; and a control device configured to control the moving device based on the information).
Consider claim 19, claim 8 of US 12,088,933 teaches (in parentheses):
A photoelectric conversion apparatus comprising: (A photoelectric conversion apparatus comprising:)
pixels disposed two-dimensionally in a row direction and a column direction, and each including a photoelectric conversion element configured to receive an incident light; (pixels disposed two-dimensionally in a row direction and a column direction, and each including a photoelectric conversion element configured to receive an incident light;)
an L number of (L is 3 or greater integer) vertical signal lines disposed on each pixel column; (an L number of (L is 3 or greater integer) vertical signal lines disposed on each pixel column;)
an M number of (M is 2 or greater integer) selection circuits disposed in each pixel, each of the selection circuits respectively connecting one of the pixels to a different vertical signal line; (an M number of (M is 2 or greater integer) selection circuits disposed in each pixel, each of the selection circuits respectively connecting one of the pixels to a different vertical signal line;)
a vertical scanning circuit configured to scan the selection circuits; (a vertical scanning circuit configured to scan the selection circuits;) and
a control unit, (a control unit)
wherein the control unit is configured to set a first operation mode in which the vertical scanning circuit performs a single read scanning operation at a time, and a second operation mode in which the vertical scanning circuit performs a plurality of read scanning operations at a time, (the control unit is configured to set a first operation mode in which the vertical scanning circuit performs a single read scanning operation at a time, and a second operation mode in which the vertical scanning circuit performs a plurality of read scanning operations at a time)
wherein, in the first operation mode, the control unit is configured to perform the single read scanning operation using a first selection circuit out of the M number of selection circuits, (in the first operation mode, the control unit is configured to perform the read scanning operation using a first selection circuit out of the M number of selection circuits) and
wherein, in the second operation mode, the control unit is configured to perform an operation which is one of the plurality of read scanning operations, using a second selection circuit, which is different from the first selection circuit, out of the M number of selection circuits (and wherein, in the second operation mode, the control unit is configured to perform the read scanning operation using a second selection circuit, which is different from the first selection circuit, out of the M number of selection circuits).
Consider claim 21, claim 8 of US 12,088,933 teaches (in parentheses):
the plurality of read scanning operations in the second operation mode include a first read scanning operation and a second read scanning operation, and wherein the second read scanning operation is performed for a plurality of times while the first read scanning operation is performed once (the plurality of read scanning operations in the second operation mode include a first read scanning operation and a second read scanning operation, and wherein the second read scanning operation is performed for a plurality of times while the first read scanning operation is performed once).
Consider claim 19, claim 11 of US 12,088,933 teaches (in parentheses):
A photoelectric conversion apparatus comprising: (A photoelectric conversion apparatus comprising:)
pixels disposed two-dimensionally in a row direction and a column direction, and each including a photoelectric conversion element configured to receive an incident light; (pixels disposed two-dimensionally in a row direction and a column direction, and each including a photoelectric conversion element configured to receive an incident light;)
an L number of (L is 3 or greater integer) vertical signal lines disposed on each pixel column; (an L number of (L is 3 or greater integer) vertical signal lines disposed on each pixel column;)
an M number of (M is 2 or greater integer) selection circuits disposed in each pixel, each of the selection circuits respectively connecting one of the pixels to a different vertical signal line; (an M number of (M is 2 or greater integer) selection circuits disposed in each pixel, each of the selection circuits respectively connecting one of the pixels to a different vertical signal line;)
a vertical scanning circuit configured to scan the selection circuits; (a vertical scanning circuit configured to scan the selection circuits;) and
a control unit, (a control unit)
wherein the control unit is configured to set a first operation mode in which the vertical scanning circuit performs a single read scanning operation at a time, and a second operation mode in which the vertical scanning circuit performs a plurality of read scanning operations at a time, (the control unit is configured to set a first operation mode in which the vertical scanning circuit performs a single read scanning operation at a time, and a second operation mode in which the vertical scanning circuit performs a plurality of read scanning operations at a time)
wherein, in the first operation mode, the control unit is configured to perform the single read scanning operation using a first selection circuit out of the M number of selection circuits, (in the first operation mode, the control unit is configured to perform the read scanning operation using a first selection circuit out of the M number of selection circuits) and
wherein, in the second operation mode, the control unit is configured to perform an operation which is one of the plurality of read scanning operations, using a second selection circuit, which is different from the first selection circuit, out of the M number of selection circuits (and wherein, in the second operation mode, the control unit is configured to perform the read scanning operation using a second selection circuit, which is different from the first selection circuit, out of the M number of selection circuits).
Consider claim 24, claim 11 of US 12,088,933 teaches (in parentheses):
the first operation mode includes a first sub-mode in which a plurality of pixel rows are read without performing analog addition on the vertical signal line, and a second sub-mode in which a plurality of pixel rows are read with performing analog addition on the vertical signal line, wherein a number of the selection circuits disposed in one pixel is at least 3, wherein, in the first sub-mode, the read scanning operation is performed for each vertical signal line using any one of the selection circuits, wherein, in the second sub-mode, the read scanning operation is performed for each vertical signal line using a plurality of selection circuits including the selection circuit used in the first sub-mode, and wherein, in the second operation mode, the read scanning operation is performed using a selection circuit other than the selection circuits used in the second sub-mode (the first operation mode includes a first sub-mode in which a plurality of pixel rows are read without performing analog addition on the vertical signal line, and a second sub-mode in which a plurality of pixel rows are read with performing analog addition on the vertical signal line, wherein a number of the selection circuits disposed in one pixel is at least 3, wherein, in the first sub-mode, the read scanning operation is performed for each vertical signal line using any one of the selection circuits, wherein, in the second sub-mode, the read scanning operation is performed for each vertical signal line using a plurality of selection circuits including the selection circuit used in the first sub-mode, and wherein, in the second operation mode, the read scanning operation is performed using a selection circuit other than the selection circuits used in the second sub-mode).
Claim 27 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of U.S. Patent No. 12,088,933 in view of Sambonsugi (US 2020/0128200).
Consider claim 27, claim 6 of US 12,088,933 teaches (in parentheses, see claims 1 and 6 of US 12,088,933):
A photoelectric conversion apparatus comprising: (A photoelectric conversion apparatus comprising:)
pixels disposed two-dimensionally in a row direction and a column direction, and each including a photoelectric conversion element configured to receive an incident light; (pixels disposed two-dimensionally in a row direction and a column direction, and each including a photoelectric conversion element configured to receive an incident light;)
an L number of (L is 3 or greater integer) vertical signal lines disposed on each pixel column; (an L number of (L is 3 or greater integer) vertical signal lines disposed on each pixel column;)
an M number of (M is 2 or greater integer) selection circuits disposed in each pixel, each of the selection circuits respectively connecting one of the pixels to a different vertical signal line; (an M number of (M is 2 or greater integer) selection circuits disposed in each pixel, each of the selection circuits respectively connecting one of the pixels to a different vertical signal line;)
a vertical scanning circuit configured to scan the selection circuits; (a vertical scanning circuit configured to scan the selection circuits;) and
a control unit, (a control unit)
wherein the control unit is configured to set a first operation mode in which the vertical scanning circuit performs a single read scanning operation at a time, and a second operation mode in which the vertical scanning circuit performs a plurality of read scanning operations at a time, (the control unit is configured to set a first operation mode in which the vertical scanning circuit performs a single read scanning operation at a time, and a second operation mode in which the vertical scanning circuit performs a plurality of read scanning operations at a time)
wherein, in the first operation mode, the control unit is configured to perform the single read scanning operation using a first selection circuit out of the M number of selection circuits, (in the first operation mode, the control unit is configured to perform the read scanning operation using a first selection circuit out of the M number of selection circuits) and
wherein, in the second operation mode, the control unit is configured to perform an operation which is one of the plurality of read scanning operations, using a second selection circuit, which is different from the first selection circuit, out of the M number of selection circuits (and wherein, in the second operation mode, the control unit is configured to perform the read scanning operation using a second selection circuit, which is different from the first selection circuit, out of the M number of selection circuits), and
a signal processing unit configured to process signals outputted from the photoelectric conversion apparatus (A photoelectric conversion system comprising: the photoelectric conversion apparatus according to claim 1; and a signal processing unit configured to process signals outputted from the photoelectric conversion apparatus).
However, claim 6 of US 12,088,933 does not explicitly teach that the signal processing unit generates a first image using the signals read out in the first operation mode, and generates a second image using the signals read out in the second operation mode.
Sambonsugi similarly teaches:
A photoelectric conversion system comprising:
a photoelectric conversion apparatus (see figures 2A and 2B);
and a signal processing unit (image processing unit, 107) configured to process signals outputted from the photoelectric conversion apparatus (“The CPU 102 transfers the inputted LV image data to the image processing unit 107, develops the LV image data in a development circuit (not illustrated) in the image processing unit 107, and starts display as a live-view image on the display unit 104.” paragraph 0110),
wherein the photoelectric conversion apparatus comprises:
pixels (200) disposed two-dimensionally in a row direction and a column direction (see figures 2A and 2B, paragraph 0036);
an L number of (L is 3 or greater integer) vertical signal lines (column output lines, 300) disposed on each pixel column (e.g. 12 column output lines (300), as shown in figures 2A and 2B, paragraph 0041);
an M number of (M is 2 or greater integer) selection circuits (selection switches, 206) disposed in each pixel (e.g. 3 selection switches (206a, 206b, 206c) disposed in each pixel (200), as shown in figure 2B, paragraph 0039), each of the selection circuits (206) respectively connecting one of the pixels (200) to a different vertical signal line (300, i.e. via output terminals 207a, 207b and 207c, respectively, figures 2A and 2B, paragraph 0041);
a vertical scanning circuit (vertical scanning circuit, 303, figure 2A) configured to scan the selection circuits (206a, 206b, 206c, i.e. by supplying control signals sel0 to sel2, figure 2B, paragraph 0041); and
a control unit (CPU, 102, figure 1, paragraph 0084),
wherein the control unit (102) is configured to set first operation mode in which the vertical scanning circuit (303) performs a single read scanning operation at a time (For instance, in the mode corresponding to frame number “LV_0” in figure 7A, a single read scanning operation for scanning only VOB_0 is performed, paragraphs 0070 and 0071.), and a second operation mode in which the vertical scanning circuit (303) performs a plurality of read scanning operations at a time (For instance, in the mode corresponding to frame number “LV_3” in figure 7B, a plurality of read scanning operations at a time are performed including a first read scanning operation for scanning VOB_0 and a second read scanning operation for scanning VOB_1, paragraphs 0070 and 0071.),
wherein, in the first operation mode (i.e. for LV_0 in figure 7A), the control unit (102) is configured to perform the single read scanning operation using a first selection circuit (206b) out of the M number of selection circuits (i.e. such that a signal is output via output terminal 207b, see figures 7A and 2B), and
wherein, in the second operation mode (i.e. for LV_3 in figure 7B), the control unit (102) is configured to perform an operation which is one of the plurality of read scanning operations, using a second selection circuit (206c), which is different from the first selection circuit, out of the M number of selection circuits (For instance, during the scanning of VOB_0, a signal is output via output terminal 207c, see figures 7B and 2B.).
However, Sambonsugi additionally teaches that the signal processing unit (107) generates a first image using the signals read out in the first operation mode, and generates a second image using the signals read out in the second operation mode (As detailed in paragraph 0110, the signal processing unit (107) develops the live view (LV) image data. As such the signal processing unit generates a first image based on frame LV_0 in figure 7A and a second image based on frame LV_3 of figure 7B, paragraphs 0107-0110 and 0126-0129.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the signal processing unit taught by claim 6 of US 12,088,933 generate first and second images as taught by Sambonsugi for the benefit of enabling a user to be provided with a displayed live view image (Sambonsugi, paragraph 0110).
Claim 28 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of U.S. Patent No. 12,088,933 in view of Sambonsugi (US 2020/0128200) and Ashida et al. (US 2013/0258134).
Consider claim 28, claim 6 of US 12,088,933 teaches (in parentheses, see claims 1 and 6 of US 12,088,933):
A photoelectric conversion apparatus comprising: (A photoelectric conversion apparatus comprising:)
pixels disposed two-dimensionally in a row direction and a column direction, and each including a photoelectric conversion element configured to receive an incident light; (pixels disposed two-dimensionally in a row direction and a column direction, and each including a photoelectric conversion element configured to receive an incident light;)
an L number of (L is 3 or greater integer) vertical signal lines disposed on each pixel column; (an L number of (L is 3 or greater integer) vertical signal lines disposed on each pixel column;)
an M number of (M is 2 or greater integer) selection circuits disposed in each pixel, each of the selection circuits respectively connecting one of the pixels to a different vertical signal line; (an M number of (M is 2 or greater integer) selection circuits disposed in each pixel, each of the selection circuits respectively connecting one of the pixels to a different vertical signal line;)
a vertical scanning circuit configured to scan the selection circuits; (a vertical scanning circuit configured to scan the selection circuits;) and
a control unit, (a control unit)
wherein the control unit is configured to set a first operation mode in which the vertical scanning circuit performs a single read scanning operation at a time, and a second operation mode in which the vertical scanning circuit performs a plurality of read scanning operations at a time, (the control unit is configured to set a first operation mode in which the vertical scanning circuit performs a single read scanning operation at a time, and a second operation mode in which the vertical scanning circuit performs a plurality of read scanning operations at a time)
wherein, in the first operation mode, the control unit is configured to perform the single read scanning operation using a first selection circuit out of the M number of selection circuits, (in the first operation mode, the control unit is configured to perform the read scanning operation using a first selection circuit out of the M number of selection circuits) and
wherein, in the second operation mode, the control unit is configured to perform an operation which is one of the plurality of read scanning operations, using a second selection circuit, which is different from the first selection circuit, out of the M number of selection circuits (and wherein, in the second operation mode, the control unit is configured to perform the read scanning operation using a second selection circuit, which is different from the first selection circuit, out of the M number of selection circuits), and
a signal processing unit configured to process signals outputted from the photoelectric conversion apparatus (A photoelectric conversion system comprising: the photoelectric conversion apparatus according to claim 1; and a signal processing unit configured to process signals outputted from the photoelectric conversion apparatus).
However, claim 6 of US 12,088,933 does not explicitly teach that the signal processing unit generates a first image using the signals read out in the first operation mode, and generates a second image using the signals read out in the second operation mode.
Sambonsugi similarly teaches:
A photoelectric conversion system comprising:
a photoelectric conversion apparatus (see figures 2A and 2B);
and a signal processing unit (image processing unit, 107) configured to process signals outputted from the photoelectric conversion apparatus (“The CPU 102 transfers the inputted LV image data to the image processing unit 107, develops the LV image data in a development circuit (not illustrated) in the image processing unit 107, and starts display as a live-view image on the display unit 104.” paragraph 0110),
wherein the photoelectric conversion apparatus comprises:
pixels (200) disposed two-dimensionally in a row direction and a column direction (see figures 2A and 2B, paragraph 0036);
an L number of (L is 3 or greater integer) vertical signal lines (column output lines, 300) disposed on each pixel column (e.g. 12 column output lines (300), as shown in figures 2A and 2B, paragraph 0041);
an M number of (M is 2 or greater integer) selection circuits (selection switches, 206) disposed in each pixel (e.g. 3 selection switches (206a, 206b, 206c) disposed in each pixel (200), as shown in figure 2B, paragraph 0039), each of the selection circuits (206) respectively connecting one of the pixels (200) to a different vertical signal line (300, i.e. via output terminals 207a, 207b and 207c, respectively, figures 2A and 2B, paragraph 0041);
a vertical scanning circuit (vertical scanning circuit, 303, figure 2A) configured to scan the selection circuits (206a, 206b, 206c, i.e. by supplying control signals sel0 to sel2, figure 2B, paragraph 0041); and
a control unit (CPU, 102, figure 1, paragraph 0084),
wherein the control unit (102) is configured to set first operation mode in which the vertical scanning circuit (303) performs a single read scanning operation at a time (For instance, in the mode corresponding to frame number “LV_0” in figure 7A, a single read scanning operation for scanning only VOB_0 is performed, paragraphs 0070 and 0071.), and a second operation mode in which the vertical scanning circuit (303) performs a plurality of read scanning operations at a time (For instance, in the mode corresponding to frame number “LV_3” in figure 7B, a plurality of read scanning operations at a time are performed including a first read scanning operation for scanning VOB_0 and a second read scanning operation for scanning VOB_1, paragraphs 0070 and 0071.),
wherein, in the first operation mode (i.e. for LV_0 in figure 7A), the control unit (102) is configured to perform the single read scanning operation using a first selection circuit (206b) out of the M number of selection circuits (i.e. such that a signal is output via output terminal 207b, see figures 7A and 2B), and
wherein, in the second operation mode (i.e. for LV_3 in figure 7B), the control unit (102) is configured to perform an operation which is one of the plurality of read scanning operations, using a second selection circuit (206c), which is different from the first selection circuit, out of the M number of selection circuits (For instance, during the scanning of VOB_0, a signal is output via output terminal 207c, see figures 7B and 2B.).
However, Sambonsugi additionally teaches that the signal processing unit (107) generates a first image using the signals read out in the first operation mode, and generates a second image using the signals read out in the second operation mode (As detailed in paragraph 0110, the signal processing unit (107) develops the live view (LV) image data. As such the signal processing unit generates a first image based on frame LV_0 in figure 7A and a second image based on frame LV_3 of figure 7B, paragraphs 0107-0110 and 0126-0129.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the signal processing unit taught by claim 6 of US 12,088,933 generate first and second images as taught by Sambonsugi for the benefit of enabling a user to be provided with a displayed live view image (Sambonsugi, paragraph 0110).
However, the combination of claim 6 of US 12,088,933 and Sambonsugi does not explicitly teach that the signal processing unit detects whether flicker is present or not using the signals read out in the second operation mode.
Ashida et al. similarly teaches a photoelectric conversion system (figure 1) comprising a signal processing unit (calculation/processing unit, 50, paragraph 0041).
However, Ashida et al. additionally teaches that the signal processing unit detects whether flicker is present or not using live view image data (“flicker detection and LED detection may be performed in a live view image, which is to be captured continuously in time immediately before a shutter switch is pressed” paragraphs 0093 and 0041).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the signals read out in the second operation mode taught by the combination of claim 6 of US 12,088,933 and Sambonsugi be used by the signal processing unit to detect whether flicker is present or not as taught by Ashida et al. for the benefit of enabling an accurate determination to be made about whether a subject including light from a flashing LED is being imaged (Ashida et al., paragraph 0012).
Allowable Subject Matter
Claims 1, 12-18, 29 and 30 are allowed.
Claims 20, 21, 23 and 24 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and upon submission of a proper Terminal Disclaimer overcoming the double patenting rejections thereof.
The following is a statement of reasons for the indication of allowable subject matter:
Consider claim 1, the closest prior art, Sambonsugi (US 2020/0128200) teaches:
A photoelectric conversion apparatus comprising:
pixels (200) disposed two-dimensionally in a row direction and a column direction (see figures 2A and 2B, paragraph 0036);
an L number of (L is 3 or greater integer) vertical signal lines (column output lines, 300) disposed on each pixel column (e.g. 12 column output lines (300), as shown in figures 2A and 2B, paragraph 0041);
an M number of (M is 2 or greater integer) selection circuits (selection switches, 206) disposed in each pixel (e.g. 3 selection switches (206a, 206b, 206c) disposed in each pixel (200), as shown in figure 2B, paragraph 0039), each of the selection circuits (206) respectively connecting one of the pixels (200) to a different vertical signal line (300, i.e. via output terminals 207a, 207b and 207c, respectively, figures 2A and 2B, paragraph 0041);
a vertical scanning circuit (vertical scanning circuit, 303, figure 2A) configured to scan the selection circuits (206a, 206b, 206c, i.e. by supplying control signals sel0 to sel2, figure 2B, paragraph 0041); and
a control unit (CPU, 102, figure 1, paragraph 0084),
wherein the control unit (102) is configured to set first operation mode in which the vertical scanning circuit (303) performs a single read scanning operation at a time (For instance, in the mode corresponding to frame number “LV_0” in figure 7A, a single read scanning operation for scanning only VOB_0 is performed, paragraphs 0070 and 0071.), and a second operation mode in which the vertical scanning circuit (303) performs a plurality of read scanning operations at a time (For instance, in the mode corresponding to frame number “LV_3” in figure 7B, a plurality of read scanning operations at a time are performed including a first read scanning operation for scanning VOB_0 and a second read scanning operation for scanning VOB_1, paragraphs 0070 and 0071.),
wherein, in the first operation mode (i.e. for LV_0 in figure 7A), the control unit (102) is configured to perform the single read scanning operation using a first selection circuit (206b) out of the M number of selection circuits (i.e. such that a signal is output via output terminal 207b, see figures 7A and 2B), and
wherein, in the second operation mode (i.e. for LV_3 in figure 7B), the control unit (102) is configured to perform an operation which is one of the plurality of read scanning operations, using a second selection circuit (206c), which is different from the first selection circuit, out of the M number of selection circuits (For instance, during the scanning of VOB_0, a signal is output via output terminal 207c, see figures 7B and 2B.), wherein,
in the first operation mode (i.e. for LV_0 in figure 7A), the single read scanning operation is performed for a range from a first row to a second row (e.g. for 6 consecutive rows in figure 7A), and
in the second operation mode (i.e. for LV_3 in figure 7B), the operation is performed for a third row and a fourth row (e.g. for rows in VOB_1 of figure 7B).
However, the prior art of record does not teach nor reasonably suggest that the third row and the fourth row are located between the first row and the second row, in combination with the other elements recited in claim 1.
Claims 12-18, 29 and 30 are allowed as depending from or otherwise requiring all of the limitations of an allowed claim 1.
Consider claim 20, the prior art of record does not teach nor reasonably suggest that the plurality of read scanning operations in the second operation mode include a first read scanning operation and a second read scanning operation, and wherein a cycle of the first read scanning operation is longer than a cycle of the second read scanning operation, in combination with the other elements recited in parent claim 19.
Consider claim 21, the prior art of record does not teach nor reasonably suggest that the plurality of read scanning operations in the second operation mode include a first read scanning operation and a second read scanning operation, and wherein the second read scanning operation is performed for a plurality of times while the first read scanning operation is performed once, in combination with the other elements recited in parent claim 19.
Consider claim 23, the prior art of record does not teach nor reasonably suggest that a number of pixel rows to be read in the first read scanning operation is larger than a number of pixel rows to be read in the second read scanning operation, in combination with the other elements recited in parent claims 22 and 19.
Consider claim 24, the prior art of record does not teach nor reasonably suggest that the first operation mode includes a first sub-mode in which a plurality of pixel rows are read without performing analog addition on the vertical signal line, and a second sub-mode in which a plurality of pixel rows are read with performing analog addition on the vertical signal line, wherein a number of the selection circuits disposed in one pixel is at least 3, wherein, in the first sub-mode, the read scanning operation is performed for each vertical signal line using any one of the selection circuits, wherein, in the second sub-mode, the read scanning operation is performed for each vertical signal line using a plurality of selection circuits including the selection circuit used in the first sub-mode, and wherein, in the second operation mode, the read scanning operation is performed using a selection circuit other than the selection circuits used in the second sub-mode, in combination with the other elements recited in parent claim 19.
Conclusion
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637