DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 10 and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 3 of U.S. Patent No. 12,096,151 (Patent ‘151, hereinafter). Although the claims at issue are not identical, they are not patentably distinct from each other because all of the features of current claims 10 and 11 are already included in claims 1 and 3 of Patent ‘151. See tables below.
Table I:
Current Application 18/802071
U.S. Patent No. 12,096,151
10, 11
1, 3, respectively
Table II:
Current Application 18/802071
U.S. Patent No. 12,096,151
10. A method for processing an image, applicable to a field programmable gate array (FPGA), comprising:
acquiring at least one channel of video data of an ultra-high-definition (UHD) video system;
generating oscillogram data based on each channel of the video data;
acquiring a pre-generated background image of an oscillogram; and
generating the oscillogram based on the background image and the oscillogram data
wherein said generating oscillogram data based on each channel of the video data comprises: counting oscillogram data of each frame image in each channel of the video data by regional counting, said counting oscillogram data of each frame image in each channel of the video data by regional counting comprises:
regionally counting the oscillogram data of each frame image in each channel of the video data by using a dual-port random access memory (RAM) and a RAM ping-pong operation mechanism;
wherein said regionally counting the oscillogram data of each frame image in each channel of the video data by using the dual-port RAM and the RAM ping-pong operation mechanism comprises:
determining, for each channel of the video data, a number of dual-port RAMs required according to a number of regions, wherein the number of dual-port RAMs required is twice the number of regions;
dividing the dual-port RAMs required into two groups; and
regionally counting the oscillogram data of each frame image in the video data by using the RAM ping-pong operation mechanism and two groups of dual-port RAMs, wherein one group of dual-port RAMs in the two groups of dual-port RAMs are configured to regionally count oscillogram data of an odd-numbered frame image in the video data, and the other group of dual-port RAMs in the two groups of dual-port RAMs are configured to regionally count oscillogram data of an even-numbered frame image in the video data.
1. A method for generating a vector diagram, applicable to a field programmable gate array (FPGA), comprising:
acquiring video data of an ultra-high-definition (UHD) video system;
regionally counting vector diagram information of each frame image in the video data by using a dual-port random access memory (RAM) and a RAM ping-pong operation mechanism;
extracting a vector diagram timing from the video data;
acquiring vector diagram data by combining the vector diagram information of each frame image with the vector diagram timing;
acquiring a pre-generated background image of a vector diagram; and
generating the vector diagram based on the background image and the vector diagram data;
wherein said regionally counting the vector diagram information of each frame image in the video data by using the dual-port RAM and the RAM ping-pong operation mechanism comprises:
determining, according to a number of regions, a number of dual-port RAMs required, wherein the number of dual-port RAMs required is twice the number of regions;
dividing the dual-port RAMs required into two groups; and
regionally counting the vector diagram information of each frame image in the video data by using the RAM ping-pong operation mechanism and two groups of dual-port RAMs, wherein one group of dual-port RAMs in the two groups of dual-port RAMs are configured to regionally count vector diagram information of an odd-numbered frame image in the video data, and the other group of dual-port RAMs in the two groups of dual-port RAMs are configured to regionally count vector diagram information of an even-numbered frame image in the video data.
From the tables above, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify claims 1 and 3 as current claims 10 and 11 since the vector diagram recited in Patent ‘151 is defined as oscillogram data in current specification, and therefore, all of the features of current claims 10 and 11 are already included in claims 1 and 3 of Patent ‘151.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8, 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (US. Patent App. Pub. No. 2011/0242333, “Zhu”, hereinafter) in view of Adams et al. (US. Patent App. Pub. No. 20140240517, “Adams”) further in view of Hartley et al. (US. Patent App. Pub. No. 20050157172, “Hartley”).
As per claim 1, Zhu teaches a method for processing an image, applicable to a field programmable gate array (FPGA) (¶ [33]), comprising:
acquiring at least one channel of video data of an ultra-high-definition (UHD) (further addressed below) video system (¶ [11], receive a first video signal associated with a first channel, a second input terminal to receive a second video signal associated with a second channel. The video is in high-definition format, ¶ [50]);
generating oscillogram data based on each channel of the video data (Fig. 3, ¶ [40], waveform monitoring for each channel. Paragraph [28] recites “the test and measurement instrument can include a waveform monitor, vectorscope, logic analyzer, or oscilloscope, among other suitable measurement devices”. The oscillogram data is interpreted as is defined at paragraph [9] of the specification of the instant application, which can be waveform diagram data or vector diagram data).
Zhu does not explicitly teach the video data is ultra-high-definition (UHD),
However, ultra-high-definition (UHD) video signals are well known in the art before the filing date of the invention. One of which is disclosed in Adams in a similar method of generating waveform over video as input video (see Abstract and ¶ [70]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use UHD video for input as taught by Adams for input video as taught by Zhu as addressed above, the advantage of which is for higher resolution video data.
The combined teachings of Zhu and Adams does not include acquiring a pre-generated background image of an oscillogram; and generating the oscillogram based on the background image and the oscillogram data.
However, in a very similar method of generating vector diagram on the video signal (see Fig. 1, ¶ [2]), Hartley teaches the above features, i.e., acquiring a pre-generated background image of an oscillogram; and generating the oscillogram based on the background image and the oscillogram data (see Fig. 2 and 3, ¶ [22] and ¶ [25], “Such control operations multiplex the picture component signal, the waveform/audio/vector displays and the background signal together to form the high resolution output video signal S' whereby the picture component signal and the waveform/audio/vector displays are superimposed onto background signal to create a display of the form shown in FIG. 1”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Hartley into the method as taught by the combined Zhu-Adams as addressed above, the advantage of which is to reduce undesirable artifacts in the processed signal (¶ [5]).
As per claim 2, as addressed above in claim 1, the combined teachings of Zhu, Adams, and Hartley also disclose acquiring at least one channel of superimposed video data by superimposing each channel of the video data with corresponding oscillogram data; and wherein said generating the oscillogram based on the background image and the oscillogram data comprises: acquiring at least one channel of video data with an oscillogram by fusing the at least one channel of superimposed video data with the background image (see Hartley, ¶ [22] and ¶ [25] recited above). Thus, claim 2 would have been obvious over the combined references for the reason above.
As per claim 3, the combined Zhu-Adams-Hartley also teaches wherein said acquiring at least one channel of video data of the UHD video system comprises:
acquiring at least two channels of video data of the UHD video system (Zhu, Fig. 3); and
said acquiring at least one channel of video data with the oscillogram by fusing the at least one channel of superimposed video data with the background image comprises:
acquiring at least two channels of video data with the oscillogram by fusing each channel of the superimposed video data with the background image (Zhu, Fig. 3, at least channel 1 and channel 2, fusing each channel of the superimposed video data with the background image as taught by Hartley as described in ¶ [25]). Thus, claim 3 would have been obvious over the combined references for the reason above.
As per claim 4, the combined Zhu-Adams-Hartley does also teach outputting the at least two channels of video data with the oscillogram, to cause a display device to display the at least two channels of video data with the oscillogram, wherein a display region of the display device comprises at least two subdisplay regions, each of the at least two subdisplay regions displaying one channel of video data with the oscillogram (display tiles as shown in Fig. 3 and 4 of Zhu).
As per claim 5, as addressed in claim 1, the combined Zhu-Adams-Hartley does also teach wherein the oscillogram data comprises at least one of vector diagram data, histogram data, and waveform diagram data (e.g., Zhu, Fig. 3).
As per claim 6, the combined Zhu-Adams-Hartley further teaches wherein the oscillogram comprises a first oscillogram and a second oscillogram that are different types (Zhu, Fig. 3, waveform, channel 1, and vector, channel 2); and
the background image comprises a plurality of regions arranged in an array, each of the plurality of regions comprises a first subregion and a second subregion, the first subregion of each of the plurality of regions is a background image of the first oscillogram, and the second subregion of each of the plurality of regions is a background image of the second oscillogram (Zhu, addressed in claim 4 with each region in combination with Hartley’s superimposing oscillogram data onto each channel of video data as addressed above). Thus, claim 6 would have been obvious over the combined references for the reason above.
As per claim 7, the combined Zhu-Adams-Hartley does not expressly teach wherein the background image is pre-stored in a system on chip (SoC), and said acquiring the pre-generated background image of the oscillogram comprises: receiving the background image from the SoC.
However, Hartley does teach generating background image (¶ [6], and [18]). Also, as shown in Fig. 3 of Hartley is the video signal processor that generates the background image (¶ 22-23]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the video processor as a system on chip (SoC) since this is well within the level of ordinary skill in the art for compacting the circuitry.
As per claim 8, the combined Zhu-Adams-Hartley does impliedly teach wherein said generating oscillogram data based on each channel of the video data comprises: counting oscillogram data of each frame image in each channel of the video data by regional counting (for example, in Zhu, Fig. 3, two diagrams for two channels of each frame having two regions. Claim is at best understood by the examiner since the counting is not clearly specified even in the current specification, i.e., it is not for counting number of oscillogram data).
As per claim 12, the combined Zhu-Adams-Hartley also teaches wherein the UHD video system is a 4k-resolution video system, a 6k-resolution video system, an 8k-resolution video system, or a 12k-resolution video system (Adams, ¶ [70]). Thus, claim 12 would have been obvious over the combined references for the reason above.
Claim 13, which is similar in scope to claim 1 as addressed above, is thus rejected under the same rationale.
Claim 14, which is similar in scope to claim 2 as addressed above, is thus rejected under the same rationale.
Claim 15, which is similar in scope to claim 3 as addressed above, is thus rejected under the same rationale.
Claim 16, which is similar in scope to claim 4 as addressed above, is thus rejected under the same rationale.
Claim 17, which is similar in scope to claim 5 as addressed above, is thus rejected under the same rationale.
Claim 18, which is similar in scope to claim 6 as addressed above, is thus rejected under the same rationale.
Claim 19, which is similar in scope to claim 7 as addressed above, is thus rejected under the same rationale.
Claim 20, which is similar in scope to claim 1 as addressed above, is thus rejected under the same rationale.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (US. Patent App. Pub. No. 2011/0242333) in view of Adams et al. (US. Patent App. Pub. No. 20140240517) further in view of Hartley et al. (US. Patent App. Pub. No. 20050157172) and further in view of Olsson et al. (US. Patent App. Pub. No. 2018/0202940, “Olsson”).
As per claim 9, the combined Zhu-Adams-Hartley does not explicitly teach wherein said counting oscillogram data of each frame image in each channel of the video data by regional counting comprises: regionally counting the oscillogram data of each frame image in each channel of the video data by using a dual-port random access memory (RAM) and a RAM ping-pong operation mechanism.
However, dual-port random access memory (RAM) and a RAM ping-pong operation mechanism is well known in the art for reading in one port and writing in the other port. One of which is described in Olsson (¶ [23]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the dual-port random access memory (RAM) and a RAM ping-pong operation mechanism as taught by Olsson in the combined Zhu-Adams-Hartley method as addressed above, the benefit of which as addressed, is for reading in one port and writing in the other port of the dual port RAM.
Allowable Subject Matter
Claims 10 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter (after the Double Patenting rejection mentioned above is resolved):
The prior art taken singly or in combination does not teach or suggest, a method for processing an image, among other things, comprising:
… wherein said regionally counting the oscillogram data of each frame image in each channel of the video data by using the dual-port RAM and the RAM ping-pong operation mechanism comprises:
determining, for each channel of the video data, a number of dual-port RAMs required according to a number of regions, wherein the number of dual-port RAMs required is twice the number of regions;
dividing the dual-port RAMs required into two groups; and
regionally counting the oscillogram data of each frame image in the video data by using the RAM ping-pong operation mechanism and two groups of dual-port RAMs, wherein one group of dual-port RAMs in the two groups of dual-port RAMs are configured to regionally count oscillogram data of an odd-numbered frame image in the video data, and the other group of dual-port RAMs in the two groups of dual-port RAMs are configured to regionally count oscillogram data of an even-numbered frame image in the video data.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hau H. Nguyen whose telephone number is: 571-272-7787. The examiner can normally be reached on MON-FRI from 8:30-5:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tammy Goddard, can be reached on (571) 272-7773.
The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAU H NGUYEN/Primary Examiner, Art Unit 2611