DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in response to the amendment filed on 02/19/2026. Claims 1 and 3-20 are pending. Claims 1, 3, 5, 9, 11-13, 16, and 19-20 are amended. Claim 2 is canceled.
Response to Arguments
Applicant's arguments filed 02/19/2026 have been fully considered but they are not persuasive.
On page 8 of the Remarks, Applicant argues that “Claim 6 addresses which addresses should be monitored, and the prediction circuitry in claim 6 predicts which addresses (the "monitored addresses") should be monitored. Those addresses, once predicted, will be monitored to determine the data values.”
However, this argument is not persuasive because claim 6 still recites “predict, as the monitored addresses, one or more future addresses”, which is still unclear because it does not make sense to predict a future address as a monitored address- either the address is monitored or it is predicted. Examiner suggests amending the claim to recite “predict one or more future addresses to be monitored” to clarify the meaning of this limitation.
On page 10 of the Remarks, Applicant submits:
In other words, Keltcher determines whether there is a load dependency from a subset of load instructions which are already identified as candidates for prefetching using a stride prefetcher 122. Thus, Keltcher's determination of the load dependency is fundamentally tied to the stride prefetcher 122 because that is how Keltcher detects load dependency.
The claimed control circuitry identifies that the predetermined condition is satisfied based on (1) an observation that the data value is dependent on a load instruction specifying a load address preceding the data dependent occurrence of the branch instruction, and (2) in response to the observation, an identification that the load address is predictable. This enables the data value dependency to be observed independently from the method by which the data value is predicted, e.g., an active striding load in Keltcher. Stated another way, control circuitry identifies that the predetermined condition is satisfied in a way that is not tied to a stride prefetching technique. This enables the prediction in claim 1 to be identified based on, for example, a fixed load address or a load address derived from a producer-consumer relationship.
However, this argument is not persuasive because it appears to only consider the identification of an active striding load as “an identification that the load address is predictable” and does not consider that the BRI of this limitation would include identifying that an active striding load is eligible for instruction injections for fetching data of a future load, which Keltcher performs based on matching a striding load with a conditional branch (i.e., in response to observing that the data value is dependent on a load instruction specifying a load address preceding the data dependent occurrence of the branch instruction) and determining that both the striding load and conditional branch have confidences that satisfy respective thresholds, see [0074]-[0075].
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites “predict, as the monitored addresses, one or more future addresses” in lines 4-5. It is unclear how the future addresses may be predicted as monitored addresses since a monitored address is not predicted. An address is either predicted or monitored, it does not make sense to predict an address as a monitored address. For purposes of examination this limitation will be interpreted as predicting future addresses that are used or monitored for prefetching.
Claims dependent on a rejected base claim are further rejected based on their dependence.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-8, 10-16, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Keltcher US 2023/0297381.
Regarding claim 1, Keltcher teaches:
1. An apparatus comprising:
processing circuitry configured to perform processing operations in response to a sequence of instructions ([0041]: the execution unit 106 (i.e., processing circuitry) executes instructions), wherein the processing circuitry is responsive to a branch instruction to determine whether a branch condition associated with the branch instruction is satisfied and, in response to the branch condition being satisfied, to trigger a non-sequential change in the processing operations to an instruction at a target address ([0053]: the condition of a branch is computed/determined during execution and if the outcome of the branch is taken then the program counter is set to an address of the branch (i.e., a target address), which triggers a non-sequential change in the processing operations of the execution unit to an instruction at the target address );
control circuitry (Fig. 3A, decode unit 104 and branch detector 302) configured to identify when an occurrence of the branch instruction is a data dependent occurrence of the branch instruction in which the branch condition has a dependency on a data value ([0071]: the branch detector determines whether the branch source register uses a load destination register, which identifies when the branch condition has a dependency on a data value), the dependency satisfying a predetermined condition ([0074]-[0075] discloses injecting instructions for fetching data of a future load based on matching a striding load with a conditional branch and both the striding load and the conditional branch having confidences that satisfy respective thresholds, which are collectively a predetermined condition that may be satisfied by the dependency), wherein the control circuitry is configured to identify that the predetermined condition is satisfied based on:
an observation that the data value is dependent on a load instruction specifying a load address preceding the data dependent occurrence of the branch instruction ([0074]-[0075]: the branch detector identifies that the predetermined condition is satisfied based on matching a striding load with a conditional branch, which includes an observation that the data value is dependent on a load instruction specifying a load address preceding the data dependent occurrence of the branch, see also [0071]); and
in response to the observation, an identification that the load address is predictable ([0074]: the identification that the active striding load has a confidence level that satisfies a first threshold is an identification that the load address is predictable, and this identification is made for an active striding load that matches a branch, which is in response to the observation that a striding load matches with a branch);
pre-computation circuitry (Fig. 3A, execution unit 106, load-store unit 108, stride prefetcher 122, tables 304/306, and branch compare unit 340) configured to perform one or more tracking operations to track the data value (the stride prefetcher tracks active striding loads by storing information about striding loads in table 304, see [0064] and [0067], which tracks the data value by tracking the address and stride used to fetch the data value, see [0075]) and to perform an outcome determination, in advance of execution of the branch instruction, of whether the branch condition will be satisfied ([0076]: an additional instruction is injected to precompute the outcome of the load dependent branch using the data of the future load, which performs a determination in advance of execution of the branch of whether the condition of the branch will be satisfied); and
prediction circuitry configured to perform a data dependent prediction of an outcome of the branch instruction in dependence on the outcome determination ([0077]-[0079]: the branch predictor (i.e., prediction circuitry) uses the precomputed outcome to predict the outcome of the branch).
Claim 19 is directed to a method performing the steps of the apparatus of claim 1 and is rejected for the same reasons as claim 1.
Claim 20 is directed to a non-transitory computer-readable medium storing code for the apparatus of claim 1 and is rejected for the same reasons as claim 1.
Regarding claim 3, Keltcher teaches:
3. The apparatus of claim 1, wherein the one or more tracking operations comprises monitoring data values stored at monitored addresses identified from one or more previously observed addresses specified as the load address by the load instruction (the stride prefetcher monitors addresses from previously observed addresses specified a load instruction with an entry in table 126, see [0047]-[0050], which also monitors the data values stored at those addresses when the data values are fetched from memory, see [0044]).
Regarding claim 4, Keltcher teaches:
4. The apparatus of claim 3, wherein the one or more tracking operations comprises monitoring access requests specifying the monitored addresses ([0063]: the stride prefetcher communicates training events each time it makes a prefetch request, which monitors access requests specifying the monitored addresses).
Regarding claim 5, Keltcher teaches:
5. The apparatus of claim 3, wherein the one or more tracking operations comprises retrieving the data values from the monitored addresses ([0044]: the prefetcher prefetches data from the monitored addresses).
Regarding claim 6, Keltcher teaches:
6. The apparatus of claim 3, comprising:
address tracking circuitry configured to identify a pattern of the one or more previously observed addresses ([0047]-[0048] describes the stride prefetcher identifying patterns in the locations that data is accessed, the associated circuitry for identifying the patterns is address tracking circuitry); and
address prediction circuitry configured to predict, as the monitored addresses, one or more future addresses based on the pattern ([0048] describes that the stride prefetcher begins prefetching data based on the stride, which predicts a future address (i.e., the address used for the prefetch) based on the identified pattern, and the associated circuitry for making the prediction is address prediction circuitry).
Regarding claim 7, Keltcher teaches:
7. The apparatus of claim 6, wherein the address tracking circuitry comprises stride identification circuitry configured to identify a stride length indicative of a distance in address space between sequential ones of the one or more previously observed addresses, and the pattern comprises an indication of the stride length ([0047]-[0048] and [0051]: the stride prefetcher identifies a stride length (stored in stride field 132) which indicates a distance in the addresses between sequential previously observed addresses and is part of the pattern of addresses identified by the stride prefetcher).
Regarding claim 8, Keltcher teaches:
8. The apparatus of claim 6, wherein the address tracking circuitry comprises sequence recognition circuitry configured to identify a repeated observation of a same sequence of the previously observed addresses, and the pattern comprises an indication of the sequence ([0047]-[0048]: the stride prefetcher identifies a repeated observation of the sequence of addresses separated by the stride, see also [0063] describing that the step size/stride communicated by the stride prefetcher is the difference between consecutive memory addresses accessed by instructions in a loop, and the stride is an indication of the pattern of the sequence of memory addresses).
Regarding claim 10, Keltcher teaches:
10. The apparatus of claim 6, comprising prefetch circuitry, wherein at least one portion of the address tracking circuitry or the address prediction circuitry is provided by the prefetch circuitry (Fig. 3A, the stride prefetcher 122 is prefetch circuitry that provides at least a portion of the address tracking circuitry and address prediction circuitry).
Regarding claim 11, Keltcher teaches:
11. The apparatus of claim 1, wherein the control circuitry is configured to determine that the predetermined condition is satisfied when a result of the load instruction is stored in a register and the branch condition is dependent on a comparison instruction specifying the register ([0071] and [0073]: the branch detector/control circuitry determines a matching destination register for a branch source register by identifying that the destination register of an active striding load is used in a compare operation/instruction that determines whether the branch condition is satisfied).
Regarding claim 12, Keltcher teaches:
12. The apparatus of claim 1, comprising:
default branch prediction circuitry configured to perform a default prediction of whether the data dependent occurrence of the branch instruction is taken or not taken ([0053]: branch predictor 136 performs default predictions of whether branches are taken or not taken); and
confidence circuitry configured to calculate a confidence level associated with the data dependent prediction ([0070]: table 306 includes a confidence field that is updated to indicate more confidence when a branch matches a striding load with an entry in table 304, which is a confidence level associated with the data dependent prediction and the associated circuitry for updating the confidence is confidence circuitry),
wherein:
the prediction circuitry is configured to determine whether the confidence level satisfies a threshold condition ([0074]-[0077] describes injecting instructions to precompute the branch outcome when the confidence satisfies a threshold condition and storing the precomputed outcomes to table 308 in the branch predictor, thus the prediction circuitry determines that the confidence level satisfies a threshold condition by receiving the precomputed outcome);
when the threshold condition is not satisfied, to determine a branch result of the branch instruction based on the default prediction ([0074]: when the threshold condition is not satisfied, the instructions for fetching future data and precomputing the branch outcome are not injected and the branch predictor performs default predictions not based on the precomputed outcome, see [0053]); and
when the threshold condition is satisfied, to override the default prediction and to determine the branch result of the branch instruction based on the data dependent prediction ([0074]-[0079]: when the threshold condition is satisfied, instructions are injected for precomputing the branch outcome which the branch predictor then uses to determine the result of the branch instead of the default prediction disclosed at [0053]).
Regarding claim 13, Keltcher teaches:
13. The apparatus of claim 1, wherein:
the control circuitry is configured to identify when a predicted sequence of occurrences of the branch instruction are data dependent occurrences of the branch instruction ([0070] describes a confidence field in table 306 of the branch detector that is updated to indicate more confidence when a received branch matches a striding load, which identifies when a predicted sequence of occurrences of the branch are data dependent); and
the pre-computation circuitry is configured to generate a sequence of data dependent determinations of whether the branch condition associated with a subset of the sequence of data dependent occurrences of the branch instruction is satisfied, wherein the subset comprises data dependent occurrences between a current non-speculative point of execution to at least a current speculative point of execution ([0079]-[0080] discloses that the branch predictor may use a precomputed outcome when it has not yet reached a future iteration of the load dependent branch (i.e., at a current speculative point) and when it has already passed the load dependent branch (i.e., at a current non-speculative point), the determinations of the precomputed outcomes that are used are determinations of whether the condition associated with the occurrences of the branch are satisfied).
Regarding claim 14, Keltcher teaches:
14. The apparatus of claim 13, wherein the pre-computation circuitry is configured to track a current determination of the sequence of data dependent determinations and to perform N future determinations, where N is a positive integer ([0070] describes a confidence field that is updated (i.e., tracked by the pre-computation circuitry) to indicate more confidence when a branch matches a striding load, each match is a current determination of the sequence of data dependent determinations and the circuitry performs N future determinations by updating the confidence until it satisfies a threshold, see [0074]).
Regarding claim 15, Keltcher teaches:
15. The apparatus of claim 14, wherein the pre-computation circuitry is configured to determine N based on at least one of: an accuracy of the sequence of data dependent determinations ([0070] describes updating the confidence and [0074] teaches that instruction injections are performed when the confidence level satisfies a threshold, by updating the confidence until it satisfies the threshold the circuitry performs N future determinations based on the accuracy/confidence of the sequence of data dependent determinations being below the threshold); and a number of cycles required by the pre-computation circuitry to perform each of the data dependent determinations.
Regarding claim 16, Keltcher teaches:
16. The apparatus of claim 1, wherein the prediction circuitry is configured to trigger retrieval of one or more blocks of instructions in dependence on an outcome of the outcome determination, the one or more blocks of instructions including a target instruction at the target address ([0054]: the predictor fetches a target instruction at the memory location/target address indicated by the branch from memory in dependence on the outcome of the prediction determination, the target instruction and any other instructions fetched from the memory location are one or more blocks of instructions).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Keltcher US 2023/0297381 in view of Wang US 2021/0096861.
Regarding claim 9, Keltcher teaches:
9. The apparatus of claim 6,
Keltcher does not teach:
wherein:
the load instruction is a consumer load instruction; and
the address tracking circuitry comprises indirect address identification circuitry configured to track, as the one or more previously observed addresses, a producer address to be used as an operand in a producer load instruction resulting in a producer result value from which a consumer load address is derived, the consumer load address to be used in the consumer load instruction resulting in a consumer result value from which the data value is derived.
However, Wang teaches training a prefetcher to prefetch for producer load instructions that produce data used by consumer load instructions, see [0012]-[0015].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Keltcher to prefetch for producer and consumer load instructions as taught by Wang. This combination would include circuitry that tracks producer addresses that are used as the operand in the producer load instruction that results in a producer result value that the consumer load address is derived, and the consumer load address is used in the consumer load instruction resulting in a consumer result value from which the data value is derived. One of ordinary skill in the art would have been motivated to make this modification to accomplish prefetching for instructions accessing objects pointed to by pointers, which increases efficiency of the processor, see Wang [0016].
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Keltcher US 2023/0297381 in view of Sassone US 2013/0185516.
Regarding claim 17, Keltcher teaches:
17. A system comprising:
Keltcher does not teach:
the apparatus of claim 1, implemented in at least one packaged chip;
at least one system component; and
a board,
wherein the at least one packaged chip and the at least one system component are assembled on the board.
However, Sassone teaches:
at least one packaged chip (Fig. 4, DSP 464 is a packaged chip since a processor is a chip);
at least one system component (Fig. 4, display controller 426 is a system component); and
a board ([0044] describes that 422 is a system-on-chip device/board),
wherein the at least one packaged chip and the at least one system component are assembled on the board (Fig. 4 shows DSP 464 and display controller 426 as part of the system-on-chip/board 422).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the apparatus of Keltcher to be implemented as a processor/packaged chip that is assembled on a system-on-chip/board with a display controller as taught by Sassone. One of ordinary skill in the art would have been motivated to make this modification to enable the apparatus to display results to a user, which would improve usability of the apparatus to the user.
Regarding claim 18, Keltcher in view of Sassone teaches:
18. A chip-containing product comprising the system of claim 17, wherein the system is assembled on a further board with at least one other product component (Sassone Fig. 4: any circuitry board that implements the display is a further board and any component on the circuitry board that implements the display is a product component).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/KASIM ALLI/Examiner, Art Unit 2182 /JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183