The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination in this application (18/802,249) filed on August 13, 2024.
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claims 1-20 are pending for consideration.
Drawings
The drawings submitted on August 13, 2024 have been considered and accepted.
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on August 13, 2024. U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 U.S.C. 112
7. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 14 and 17 are rejected under 35 U.S.C. 112 (b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “original data”, claims are rejected under 35 U.S.C 112(b) as it is unclear how the data being original and what determines an original data or non-original data.
Claim 2 is rejected under 35 U.S.C. 112 (b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “the same size”, claims are rejected under 35 U.S.C 112(b) as there is an insufficient antecedent basis for this limitation.
Claim 12 recites “data chunks associated with original data”, where it is unclear how the chunks are associated with the original data as it was clearly described in the claims.
Claim 2 is rejected under 35 U.S.C. 112 (b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “the same size”, claims are rejected under 35 U.S.C 112(b) as there is an insufficient antecedent basis for this limitation. Claim further recites “a number of the first sub-block….a number of the second sub-block”.\, where it is unclear if the number refers to multiple sub-blocks, blocks, pages or else.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10 and 12-19 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Gopalakrishnan et al. (US PGPUB 2021/0096948) (hereinafter ‘Gopalakrishnan’).
As per independent claim 1, Gopalakrishnan discloses a storage device, comprising: a non-volatile memory device comprising a plurality of memory blocks in which a plurality of cell strings are divided into a plurality of sub-blocks disposed in a vertical direction [(Paragraphs 0050-0051; Figs. 1-3) where Gopalakrishnan teaches where the memory structure 326 comprises a monolithic three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells of memory structure 326 comprise vertical NAND strings with charge-trapping material such as described, for example, in U.S. Pat. No. 9,721,662, incorporated herein by reference in its entirety. In another embodiment, memory structure 326 comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates such as described, for example, in U.S. Pat. No. 9,082,502, incorporated herein by reference in its entirety to correspond to the claimed limitation], wherein in each of the plurality of cell strings, a string select transistor, a plurality of memory cells and a ground select transistor are disposed in series, in the vertical direction, between a bit line and a source line [(Paragraphs 0050-0052; Figs. 1-3) where Gopalakrishnan teaches examples of suitable technologies for architectures of memory structure 326 that include two dimensional arrays, three dimensional arrays, cross-point arrays, stacked two dimensional arrays, vertical bit line arrays, and the like. One example of a ReRAM, or PCMRAM, cross point memory includes reversible resistance-switching elements arranged in cross point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements to correspond to the claimed limitation]; and a storage controller configured to program original data into at least one first sub-block of the plurality of sub-blocks in a first level cell mode [(Paragraphs 0108-0114; Figs. 1-3) where Gopalakrishnan teaches where the ECC engines 226/256 produce a corrected version of the SLC data, based on the codeword that was read from the SLC memory cells. For the sake discusses process 800, it will be assumed that the ECC algorithm is able to correct any errors in the SLC data. Herein, techniques are discussed for recovering the SLC data in the event that the ECC algorithm (e.g., ECC engines 226/256) are not able to decode, correct, or recover the SLC data to correspond to the claimed limitation], and program recovery data for recovering the original data into at least one second sub-block of the plurality of sub-blocks in a second level cell mode having a bit density greater than that of the first level cell mode, in a first memory block of the plurality of memory blocks [(Paragraphs 0113-0118 and 0120-0123; Figs. 1-3) where Gopalakrishnan teaches where the using the stored recovered unit of SLC data during another phase of the program operation of folding the SLC data to MLC data. In one embodiment, the stored recovered unit of SLC data is used during a fine programing phase of folding the SLC data to MLC data. Step 1110 may include accessing the address of where the recovered unit of SLC data was stored (which was saved in step 1108). The stored recovered unit of SLC data may be preserved and used again in the event that there is a program failure when performing the SLC to MLC programming operation. If there is a program failure when programming MLC data during the folding operation, then the MLC data may be programmed to a different location, such as a different block of memory cells. The stored recovered unit of SLC data may be used again during this effort to program the MLC data in another location to correspond to the claimed limitation].
As per dependent claim 2, Gopalakrishnan discloses wherein the plurality of sub-blocks of the plurality of memory blocks have the same size, and a ratio of the bit density of the second level cell mode to the bit density of the first level cell mode is inversely proportional to a ratio of a number of the second sub-block to a number of the first sub-block [(Paragraphs 0113-0118 and 0120-0123; Figs. 1 and 12) where Gopalakrishnan teaches where the process 1200 will be discussed with reference to FIG. 12B. FIG. 12B depicts four SLC blocks 1222a, 1222b, 1222c, and 1222d of non-volatile memory cells that stored SLC data, as well as one MLC block 1224 of non-volatile memory cells that stores MLC data. In this example, four bits are stored per memory cell in the MLC block 1224. In one embodiment, the four SLC blocks 1222a, 1222b, 1222c, and 1222d are each on a different memory die 300. In one embodiment, the four SLC blocks 1222a, 1222b, 1222c, and 1222d are the same memory die 300. The MLC block 1224 may be on the same memory die 300 as one or more of the SLC blocks 1222b, or may be on a different memory die 300 than all of the SLC blocks 1222a-1222d. Note that herein, the reference numeral 1222 may be used to refer to an SLC block in general, without reference to a specific SLC block to correspond to the claimed limitation].
As per dependent claim 3, Gopalakrishnan discloses wherein the at least one first sub-block comprises three first sub-blocks, and the at least one second sub-block comprises one second sub-block, and the first level cell mode is a single level cell (SLC) mode, and the second level cell mode is a triple level cell (TLC) mode [(Paragraphs 0061, 0113-0118 and 0120-0123; Figs. 1-3) where Gopalakrishnan teaches where FIG. 4A illustrates example threshold voltage distributions (ranges) for MLC memory cells that store three bits of data. Other embodiments, however, may use other data capacities per memory cell (e.g., such as one, two, four, or five bits of data per memory cell). FIG. 4A shows eight threshold voltage distributions, corresponding to eight data states. The first threshold voltage distribution (data state) S0 represents memory cells that are erased. The other seven threshold voltage distributions (data states) S1-S7 represent memory cells that are programmed and, therefore, are also called programmed states; the using the stored recovered unit of SLC data during another phase of the program operation of folding the SLC data to MLC data. In one embodiment, the stored recovered unit of SLC data is used during a fine programing phase of folding the SLC data to MLC data. Step 1110 may include accessing the address of where the recovered unit of SLC data was stored (which was saved in step 1108). The stored recovered unit of SLC data may be preserved and used again in the event that there is a program failure when performing the SLC to MLC programming operation. If there is a program failure when programming MLC data during the folding operation, then the MLC data may be programmed to a different location, such as a different block of memory cells. The stored recovered unit of SLC data may be used again during this effort to program the MLC data in another location to correspond to the claimed limitation].
As per dependent claim 4, Gopalakrishnan discloses , wherein the at least one first sub-block comprises four first sub-blocks, and the at least one second sub-block comprises one second sub-block, and the first level cell mode is a SLC mode, and the second level cell mode is a quadruple level cell (QLC) mode [(Paragraphs 0113-0118 and 0120-0123; Figs. 1 and 12) where Gopalakrishnan teaches where the process 1200 will be discussed with reference to FIG. 12B. FIG. 12B depicts four SLC blocks 1222a, 1222b, 1222c, and 1222d of non-volatile memory cells that stored SLC data, as well as one MLC block 1224 of non-volatile memory cells that stores MLC data. In this example, four bits are stored per memory cell in the MLC block 1224. In one embodiment, the four SLC blocks 1222a, 1222b, 1222c, and 1222d are each on a different memory die 300. In one embodiment, the four SLC blocks 1222a, 1222b, 1222c, and 1222d are the same memory die 300. The MLC block 1224 may be on the same memory die 300 as one or more of the SLC blocks 1222b, or may be on a different memory die 300 than all of the SLC blocks 1222a-1222d. Note that herein, the reference numeral 1222 may be used to refer to an SLC block in general, without reference to a specific SLC block to correspond to the claimed limitation].
As per dependent claim 5, Gopalakrishnan discloses wherein the storage controller is configured to program two or more sets of recovery data into the at least one second sub-block [(Paragraphs 0116-0121; Figs. 1 and 11) where Gopalakrishnan teaches where the FIG. 11 is a flowchart of one embodiment of a process 1100 of using recovered UECC SLC data when folding SLC data to MLC data. In one embodiment, the process 1100 is performed by the controller 102. In one embodiment, the process 1100 is performed by storage device 100. Step 1102 includes reading a selected unit of encoded SLC data during a programming phase of an SLC data to MLC data folding operation. Step 1110 includes using the stored recovered unit of SLC data during another phase of the program operation of folding the SLC data to MLC data. In one embodiment, the stored recovered unit of SLC data is used during a fine programing phase of folding the SLC data to MLC data to correspond to the claimed limitation].
As per dependent claim 6, Gopalakrishnan discloses wherein the plurality of sub-blocks in the plurality of memory blocks have the same size, a number of the at least one first sub-block is the same as a number of the at least one second sub-block, in the first memory block, and a number of sets of the recovery data programmed in the at least one second sub-block is determined based on a ratio of the bit density of the second level cell mode to the bit density of the first level cell mode [(Paragraphs 0061, 0113-0118 and 0120-0123; Figs. 1-3) where Gopalakrishnan teaches where FIG. 4A illustrates example threshold voltage distributions (ranges) for MLC memory cells that store three bits of data. Other embodiments, however, may use other data capacities per memory cell (e.g., such as one, two, four, or five bits of data per memory cell). FIG. 4A shows eight threshold voltage distributions, corresponding to eight data states. The first threshold voltage distribution (data state) S0 represents memory cells that are erased. The other seven threshold voltage distributions (data states) S1-S7 represent memory cells that are programmed and, therefore, are also called programmed states; the using the stored recovered unit of SLC data during another phase of the program operation of folding the SLC data to MLC data. In one embodiment, the stored recovered unit of SLC data is used during a fine programing phase of folding the SLC data to MLC data. Step 1110 may include accessing the address of where the recovered unit of SLC data was stored (which was saved in step 1108). The stored recovered unit of SLC data may be preserved and used again in the event that there is a program failure when performing the SLC to MLC programming operation. If there is a program failure when programming MLC data during the folding operation, then the MLC data may be programmed to a different location, such as a different block of memory cells. The stored recovered unit of SLC data may be used again during this effort to program the MLC data in another location to correspond to the claimed limitation].
As per dependent claim 7, Gopalakrishnan discloses wherein when the first level cell mode is an SLC mode and the second level cell mode is a TLC mode, the storage controller is configured to program three sets of the recovery data into the at least one second sub-block [(Paragraphs 0061, 0113-0118 and 0120-0123; Figs. 1-3) where Gopalakrishnan teaches where FIG. 4A illustrates example threshold voltage distributions (ranges) for MLC memory cells that store three bits of data. Other embodiments, however, may use other data capacities per memory cell (e.g., such as one, two, four, or five bits of data per memory cell). FIG. 4A shows eight threshold voltage distributions, corresponding to eight data states. The first threshold voltage distribution (data state) S0 represents memory cells that are erased. The other seven threshold voltage distributions (data states) S1-S7 represent memory cells that are programmed and, therefore, are also called programmed states; the using the stored recovered unit of SLC data during another phase of the program operation of folding the SLC data to MLC data. In one embodiment, the stored recovered unit of SLC data is used during a fine programing phase of folding the SLC data to MLC data. Step 1110 may include accessing the address of where the recovered unit of SLC data was stored (which was saved in step 1108). The stored recovered unit of SLC data may be preserved and used again in the event that there is a program failure when performing the SLC to MLC programming operation. If there is a program failure when programming MLC data during the folding operation, then the MLC data may be programmed to a different location, such as a different block of memory cells. The stored recovered unit of SLC data may be used again during this effort to program the MLC data in another location to correspond to the claimed limitation].
As per dependent claim 8, Gopalakrishnan discloses wherein when the first level cell mode is an SLC mode and the second level cell mode is a QLC mode, the storage controller is configured to program four sets of the recovery data into the at least one second sub-block [(Paragraphs 0113-0118 and 0120-0123; Figs. 1 and 12) where Gopalakrishnan teaches where the process 1200 will be discussed with reference to FIG. 12B. FIG. 12B depicts four SLC blocks 1222a, 1222b, 1222c, and 1222d of non-volatile memory cells that stored SLC data, as well as one MLC block 1224 of non-volatile memory cells that stores MLC data. In this example, four bits are stored per memory cell in the MLC block 1224. In one embodiment, the four SLC blocks 1222a, 1222b, 1222c, and 1222d are each on a different memory die 300. In one embodiment, the four SLC blocks 1222a, 1222b, 1222c, and 1222d are the same memory die 300. The MLC block 1224 may be on the same memory die 300 as one or more of the SLC blocks 1222b, or may be on a different memory die 300 than all of the SLC blocks 1222a-1222d. Note that herein, the reference numeral 1222 may be used to refer to an SLC block in general, without reference to a specific SLC block to correspond to the claimed limitation].
As per dependent claim 9, Gopalakrishnan discloses wherein the recovery data is mirrored data from which the original data is copied, and when a unit data that can be programmed into one physical page of the at least one second sub-block in the second level cell mode is programmed into the at least one first sub-block, the storage controller is configured to program mirrored data copying the unit data into the at least one second sub-block [(Paragraphs 0033-0035, 0091, 0113-0118 and 0120-0123; Figs. 1-3) where Gopalakrishnan teaches where It is possible for the decoding process to fail to successfully decode the codeword, which is referred to herein as an uncorrectable ECC failure (or UECC). In one embodiment, in the event that the codeword is uncorrectable by ECC, redundancy data is used to recover the codeword. The redundancy data for a group of pages may be generated by XOR engine 224/254. In one embodiment, the redundancy data for the group of pages is stored in non-volatile memory cells in the memory structure 326 to correspond to the claimed limitation].
As per dependent claim 10, Gopalakrishnan discloses wherein the recovery data is mirrored data from which the original data is copied, and the storage controller is configured to obtain the original data from the at least one first sub-block, and when an error correction of the obtained original data is not possible, to recover the original data by obtaining mirrored data from the at least one second sub-block [(Paragraphs 0033-0035, 0091, 0113-0118 and 0120-0123; Figs. 1-3) where Gopalakrishnan teaches where It is possible for the decoding process to fail to successfully decode the codeword, which is referred to herein as an uncorrectable ECC failure (or UECC). In one embodiment, in the event that the codeword is uncorrectable by ECC, redundancy data is used to recover the codeword. The redundancy data for a group of pages may be generated by XOR engine 224/254. In one embodiment, the redundancy data for the group of pages is stored in non-volatile memory cells in the memory structure 326 to correspond to the claimed limitation].
As per dependent claim 12, Gopalakrishnan discloses wherein the recovery data is parity data of the original data, and the storage controller is configured to obtain the original data from the at least one first sub-block, recover original data chunks associated with the original data from the at least one first sub-block when an error correction of the obtained original data is not possible, obtain parity data chunks associated with the original data from the at least one second sub-block, and recover the original data by using the original data chunks and the parity data chunks [(Paragraphs 0032, 0085 and 0090) where Gopalakrishnan teaches where the controller 102 (e.g., by ECC engines 226/256) receives the codeword Y1 and accesses the LLRs and iterates in successive iterations in which it determines if parity checks of the error encoding process have been satisfied. If all parity checks have been satisfied, the decoding process has converged and the codeword has been successfully error corrected (decoded). If one or more parity checks have not been satisfied, the decoder will adjust the LLRs of one or more of the bits which are inconsistent with a parity check and then reapply the parity check or next check in the process to determine if it has been satisfied. For example, the magnitude and/or polarity of the LLRs can be adjusted. If the parity check in question is still not satisfied, the LLR can be adjusted again in another iteration. Adjusting the LLRs can result in flipping a bit (e.g., from 0 to 1 or from 1 to 0) in some, but not all, cases. In one embodiment, another parity check is applied to the codeword, if applicable, once the parity check in question has been satisfied. In others, the process moves to the next parity check, looping back to the failed check at a later time. The process continues in an attempt to satisfy all parity checks. Thus, in one embodiment, the decoding process of Y1 is completed to obtain the decoded information including parity bits v and the decoded information bits i. As part of the decoding process, controller tracks how many bits needed to be flipped, which is an indication of the number of errors in the information sensed from the memory cells. This indication of error is also referred to as bit error rate (BER) to correspond to the claimed limitation].
As per dependent claim 13, Gopalakrishnan discloses wherein the original data is metadata [(Paragraphs 0032, 0085 and 0090) where Gopalakrishnan teaches where the both SLC data and MLC data are encoded into what are referred to as “codewords” prior to storage. In one embodiment, Error Correction Codes (ECC) are used to protect SLC data from corruption. In one embodiment, the ECC are “systematic,” in that the SLC data portion of the eventual codeword is unchanged from the actual SLC data being encoded, with the ECC bits appended to the SLC data bits to form the complete codeword. Other techniques can be used that map SLC data to a codeword in more complex manners. For example, low density parity check (LDPC) codes, also referred to as Gallager codes, can be used. In either case, an ECC algorithm may be used to decode the codeword and to correct any errors in the SLC data to correspond to the claimed limitation].
As for independent claims 14 and 17, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
As for dependent claim 15, the applicant is directed to the rejections to claim 2 set forth above, as they are rejected based on the same rationale.
As for dependent claims 16 and 18, the applicant is directed to the rejections to claim 3 set forth above, as they are rejected based on the same rationale.
As for dependent claim 19, the applicant is directed to the rejections to claim 10 set forth above, as they are rejected based on the same rationale.
a(2) CLAIMS ALLOWED IN THE APPLICATION
Per the instant office action, claims 11 and 20, but would be allowable if rewritten in an independent form and overcome 112 rejections.
The reasons for allowance of claim 11 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the storage controller is configured to determine a first relative address indicating a sequence of a first physical page, into which the original data is programmed, in the at least one first sub-block, determine a ratio of a space capacity of the original data to a space capacity of the mirrored data, calculate a second address indicating a sequence of a second physical page, into which the mirrored data is programmed, in the at least one second sub-block based on the first relative address and the ratio of the space capacity, and obtain the mirrored data from the second physical page using the second address”.
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li et al., US PGPUB 2026/0037369– teaches HANDLING READ FAILURE IN ZONE MEMORY SYSTEM.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jared Ian Rutz whose telephone number is (571)272-5535. The examiner can normally be reached on Monday-Friday, 8:00 AM to 4:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135