DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continuity
Examiner notes this application is a continuation of 17/831,028.
Claim Objections
Claims 2, 4-6, 12 and 14-16 are objected to because of the following informalities:
In claim 2, “a enabling/disabling unit” should be ‘an enabling/disabling unit’.
In claim 4, “a enabling/disabling unit” should be ‘an enabling/disabling unit’.
In claim 5, “the phase shift amount” lacks antecedent basis. It appears claim 5 was intended to depend from claim 4.
In claim 6, “the phase shift amount” lacks antecedent basis. It appears claim 5 was intended to depend from claim 4.
In claim 12, “a enabling/disabling unit” should be ‘an enabling/disabling unit’.
In claim 14, “a enabling/disabling unit” should be ‘an enabling/disabling unit’.
In claim 15, “the phase shift amount” lacks antecedent basis. It appears claim 5 was intended to depend from claim 14.
In claim 16, “the phase shift amount” lacks antecedent basis. It appears claim 5 was intended to depend from claim 14.
Appropriate correction is required.
Response to Arguments
Applicant’s arguments, filed 7/24/2026, with respect to the indefiniteness rejections have been fully considered and are persuasive. The amendments have addressed the previous indefiniteness rejections.
Applicant's arguments filed 7/24/2026 with respect to the prior art rejections have been fully considered but they are not persuasive. Applicant argues Chen needs to calculate and determine the length of Toff_bs while the converter is operating, indicating that the duration of Toff_bs is not preset at the outset based on the capacitance of the bootstrap capacitor. This is incorrect; as described in paragraph 42 of the Chen reference, the duration of Toff_bs is preset by loading the count value into the 10 bit counter. The off time in burst mode is then equal to the counter value multiplied by the counting clock period, for instance, 100 μs as described in paragraph 42. Before operation, the counter time is pre-programmed with the off time duration based on the expected hold up time of the bootstrap capacitor plus the desired safety margin. There is no adjustment according to the current charge state of the bootstrap capacitor as Applicant incorrectly states. As shown in Figure 10, when the counter time expires at the end of Toff_bs, it is time to recharge the bootstrap capacitor and the Ton_bs pulse is generated to recharge the bootstrap capacitor. This is also shown in Figure 7 where the state St1 is maintained for count time Toff_burst COUNT.
Applicant contends the timing of entering the first time period T1 in the application, is unrelated to the output voltage Vo. Applicant incorrectly states this is entirely different from the features in Chen. As used in the rejection of the present claim language (original claim 7), the first time period of Ton_bs is entered upon the expiration of the Toff_bs time duration, as shown in Figures 10 and 7, when the count value of the off time duration has counted to zero. The burst period time in the Chen reference operates in the same open loop manner as Applicant’s invention. In the Chen reference even the burst period is begun when the current decreases below the vcson threshold, and is not based on the output voltage.
Applicant argues Chen does not disclose the time length of the first time period and the second time period can be determined based on the capacity of the second capacitor C2, which belongs to an open-loop control. Yet the Chen reference operates in the similar manner with the burst period (second period) being set in an open loop manner by programming the down counter with the desired burst period time (see paragraph 42 regarding Toff_bs). Likewise, the Chen reference operates in the similar manner with the bootstrap period (first period) being set in an open loop manner by programming another down counter with the desired recharge time (see paragraph 42 regarding Ton_bs where the counter may be set to 20 μs for example). The time periods of both counters are preset based on the capacity of the bootstrap capacitor, because the second period (off time) is the time the bootstrap capacitor must hold-up the bootstrap voltage and the hold-up time depends on the capacity of the bootstrap capacitor. Likewise, the first period (recharge time) is the charging time of the bootstrap capacitor, and the charging time depends on the capacity of the bootstrap capacitor.
Applicant states Kohara has disclosed that Figure 6 represent prior art, which suffers from the problem of insufficient voltage across the bootstrap capacitors causing the upper switching elements to fail to turn on. While Kohara’s Figure 6 does describe prior art, it is misleading to state Figure 6 suffers from insufficient voltage across the bootstrap capacitors, and it is more appropriate and accurate to state there is a possibility the bootstrap capacitors could be insufficiently charged. The same risk applies to all open loop charging, including Applicant’s invention. In any event, the rejection of amended claim 1 (original claim 7) relies on Chen for teaching the second period. Chen minimizes the risk by limiting the off time to a maximum countdown time of the second period, and then forcing a recharge of the first period, which is also how Applicant’s first and second periods operate, and there is not additional risk of the bootstrap capacitor discharging using Chen’s method. Examiner reiterates the secondary reference Chen is relied upon for teaching the time length of the first time period and the second period can be determined based on the capacity of the bootstrap capacitor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8, 10-13, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kohara (US 2019/0341854) in view of Chen (US 2020/0266704).
With respect to claim 1, Kohara discloses a bridge converter (Fig. 1 100), configured to convert an input voltage (Fig. 1 Vd) for providing an output voltage (Fig. 1 voltage T1 to T2) to a load (Fig. 1 LOAD), comprising: a switching circuit (Fig. 1 13) comprising a first bridge arm (Fig. 1 Q1,Q2) wherein the first bridge arm comprises a first switch (Fig. 1 Q1) and a second switch (Fig. 1 Q2) connected in series; a rectifying circuit (Fig. 1 15) configured to be coupled to the load; a transformer (Fig. 1 14) comprising a primary side (Fig. 1 left side) coupled to the switching circuit and a secondary side coupled to the rectifying circuit; a control unit (Fig.1 10) providing a first control signal (Fig. 1 U1) and a second control signal (Fig. 1 U2) for respectively controlling the first switch and the second switch based on the output voltage; and a drive module (Fig.1 11,Da,Ra,12 Db,Rb) coupled to the control unit and the switching circuit for driving the switching circuit to converting the input voltage; wherein when a loading of the load is lower than a predetermined level (Fig. 6 LOAD CURRENT decreases below the BURST MODE threshold), the control unit fixes operation frequencies of the first control signal and the second control signal at a maximum frequency (Fig. 6 U1,U2 ON/OFF switching frequency), controls the drive module to drive the first switch and the second switch respectively according to the first control signal and the second control signal in a first time period (Fig. 6 β), and disables the drive module to not drive the first switch and the second switch in a second time period (Fig. 6 α); wherein the switching circuit is configured to be coupled to a capacitor (Fig. 1 Ca); the control unit controls the drive module and the switching circuit to charge the capacitor in the first time period (Fig. 1 Da charges Ca while Q2 is low) and controls the drive module and the switching circuit not to charge the capacitor in the second time period (Fig. 1 Q2 off), and the control module determines the second time period to be less than or equal to a maximum time period (Fig. 6 time α). While Kohara remains silent as to the determination of the second time period, Examiner believes the second time period was determined based on a capacitance of the capacitor, since it was well known before the effective filing date of the claimed invention that the capacitor will discharge during the second time period and the hold up time of the capacitor will depend upon its capacitance. Additionally, Kohara discloses wherein the first time period lasts the duration β (Fig. 6 β), but does not explicitly state the time period is a fixed duration.
Chen discloses wherein the control module determines the second time period to be less than or equal to a maximum time period (Fig 10 Toff_bs) determined based on a capacitance (Fig. 1 C5 capacitance determines the hold up time) of the capacitor (Fig. 7 ST1 COUNT selected to prevent bootstrap capacitor C5 from discharging too low). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the control module determines the second time period to be less than or equal to a maximum time period determined based on a capacitance of the capacitor, in order to prevent the capacitor from discharging too low and preventing turn on of the first transistor.
Chen also discloses wherein the first time period is fixed (Fig. 7 St2 Tcbs_chg COUNT) and determined based on the capacitance of the capacitor (Fig. 10 ON/OFF for the fixed period to ensure the capacitor is charged). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the first time period is fixed and determined based on the capacitance of the capacitor, in order to ensure the capacitor is sufficiently charged.
With respect to claim 2, Kohara in view of Chen make obvious the bridge converter of claim 1, wherein the control unit further comprises: a signal modulation unit (Fig. 1 component of 10 modulating U1-U4), configured to modulate (Fig. 6 Q1-Q4 modulated) the first control signal and the second control signal complemented (Fig. 2 U2 on when U1 off; Fig. 4 U1 on when U2 OFF) to each other; and an enabling/disabling unit (Fig. 1 unit of 10 to turn Q1-Q4 OFF during α), configured to enable the drive module to drive the switching circuit in the first time period (Fig. 6 Q1,Q2 ON/OFF during β) and to disable the drive module to not drive the switching circuit in the second time period (Fig. 6 Q1,Q2 OFF during α).
With respect to claim 3, Kohara in view of Chen make obvious the bridge converter of claim 1, wherein the switching circuit further comprises a second bridge arm (Fig. 1 Q3,Q4) connected in parallel to the first bridge arm, and the second bridge arm comprises a third switch (Fig. 1 Q3 or Q4) and a fourth switch (Fig. 1 Q4 or Q3) connected in series; the control unit provides a third control signal (Fig. 1 U3 or U4) and a fourth control signal (Fig. 1 U4 or U3) for respectively controlling the third switch and the fourth switch circuit based on the output voltage; when the loading of the load is lower than the predetermined level (Fig. 6 LOAD CURRENT below BURST MODE level), the control unit fixes operation frequencies of the first control signal, the second control signal, the third control signal and the fourth control signal at the maximum frequency (Fig. 6 switching frequency), controls the drive module (Fig. 1 11,12) to drive the first switch, the second switch, the third switch and the fourth switch respectively according to the first control signal, the second control signal, the third control signal and the fourth control signal in the first time period (Fig. 6 β), and disables the drive module to not drive the first switch, the second switch, the third switch and the fourth switch in the second time period (Fig. 6 α).
With respect to claim 8, Kohara in view of Chen make obvious the bridge converter of claim 1, wherein the second time period lasts the duration β (Fig. 6 β). Kohara does not explicitly state the time duration is fixed.
Chen discloses wherein the second time period is fixed (Fig. 7 St1 Toff_burst COUNT) and determined based on the capacitance of the capacitor (Fig. 10 OFF for a maximum time Toff_bs to ensure the capacitor is not discharged). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the second time period is fixed and determined based on the capacitance of the capacitor, in order to prevent the capacitor from becoming discharged.
With respect to claim 10, Kohara in view of Chen make obvious the bridge converter of claim 1, wherein the rectifying circuit is coupled to the load without an ORing FET (Fig. 1 15 directly connected to LOAD at T1,T2).
With respect to claims 11-13, 18 and 20, Kohara in view of Chen make obvious the method as set forth above. See claims 1-3, 8 and 20, respectively, for additional details.
Claim(s) 4-6 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kohara (US 2019/0341854) in view of Chen (US 2020/0266704) and further in view of Shoji (US 2006/0139823).
With respect to claim 4, Kohara in view of Chen make obvious the bridge converter of claim 3 as set forth above, and further discloses an enabling/disabling unit, configured to enable the drive module to drive the switching circuit in the first time period (Fig. 6 Q1-Q4 turned ON/OFF during β) and to disable the drive module to not drive the switching circuit in the second time period (Fig. 6 Q1-Q4 OFF during α). Kohara remains silent as to the control technique of the switching circuit. The use of phase shift control was well known before the effective filing date of the claimed invention.
Shoji discloses wherein the control unit further comprises: a signal modulation unit (Fig. 3 generates Vg(1) – Vg(4)), configured to modulate the first control signal and the second control signal complemented to each other (Fig. 3 Vg(1) and Vg(2) are complementary), to modulate the third control signal and the fourth control signal complemented (Fig. 3 Vg(3) and Vg(4) complementary), to modulate the first control signal and the fourth control signal to have a phase-shift amount (Fig. 3 (a)), and to modulate the second control signal and the third control signal to have the phase-shift amount (Fig. 3 (c)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the control unit further comprises: a signal modulation unit, configured to modulate the first control signal and the second control signal complemented to each other, to modulate the third control signal and the fourth control signal complemented, to modulate the first control signal and the fourth control signal to have a phase-shift amount, and to modulate the second control signal and the third control signal to have the phase-shift amount; and a shielding unit, configured to enable the drive module to drive the switching circuit in the first time period and to disable the drive module to not drive the switching circuit in the second time period, in order to regulate the output voltage to the desired reference level.
With respect to claim 5, Kohara in view of Chen make obvious the bridge converter as set forth above. Kohara remains silent as to the control technique of the switching circuit. The use of phase shift control was well known before the effective filing date of the claimed invention.
Shoji discloses wherein the control unit controls the first control signal to lead the fourth control signal (Fig. 3 Vg(3)) with the phase-shift amount (Fig. 3 (a)), and controls the second control signal to lead the third control signal (Fig. 3 Vg(3)) with the phase-shift amount (Fig. 3 (c)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the control unit controls the first control signal to lead the fourth control signal with the phase-shift amount, and controls the second control signal to lead the third control signal with the phase-shift amount, in order to take advantage of phase shift control to regulate the output voltage to the desired reference level.
With respect to claim 6, Kohara in view of Chen make obvious the bridge converter as set forth above. Kohara remains silent as to the control technique of the switching circuit. The use of phase shift control was well known before the effective filing date of the claimed invention.
Shoji discloses wherein the control unit controls the first control signal to lag (Fig. 3 (d)) the fourth control signal with the phase-shift amount, and controls the second control signal to lag (Fig. 3 (b)) the third control signal with the phase-shift amount.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the control unit controls the first control signal to lag the fourth control signal with the phase-shift amount, and controls the second control signal to lag the third control signal with the phase-shift amount, in order to take advantage of phase shift control to regulate the output voltage to the desired reference level.
With respect to claims 14-16, Kohara in view of Chen and Shoji make obvious the method as set forth above. See claims 4-6, respectively, for additional details.
Claim(s) 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kohara (US 2019/0341854) in view of Chen (US 2020/0266704) and further in view of Leach (US 2007/0190369).
With respect to claim 9, Kohara in view of Chen make obvious the bridge converter of claim 1 as set forth above, and do not disclose wherein the rectifying circuit is coupled to the load through an ORing FET.
Leach discloses wherein the converter (Fig. 1 104) is coupled to the load (Fig. 1 LOAD) through an ORing FET (Fig. 1 S2, paragraph 76). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the rectifying circuit is coupled to the load through an ORing FET, in order to protect the load and converter during a fault condition.
With respect to claim 19, Kohara in view of Chen and Leach make obvious the method as set forth above. See claim 9 for additional details.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HARRY R BEHM/Primary Examiner, Art Unit 2838
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