Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 8 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 9-15 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al., US Patent Application, (20250356892), hereinafter “Park” and Shi et al., US Patent Application, (20240063092), hereinafter “Shi”
Regarding claim 1 Park teaches a semiconductor package, a semiconductor package, [Park para 0216] comprising: an interposer The interposer 1300 may connect the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the SoC 1200 and may provide physical paths formed by using conductive materials [Park para 0223] including a plurality of multiplexers (MUX) integrally formed within the interposer and electrically coupled to the plurality of MUX a semiconductor package 1000 may include a stacked memory device 1100, a system on a chip (SoC) 1200, an interposer 1300, and a package substrate 1400. The stacked memory device 1100 may include a buffer die 1110 and a plurality of core dies (e.g., a first core die 1120, a second core die 1130, a third core die 1140, and a fourth core die 1150). [Park Para 0216]; and
Park does no teach but Shi teaches and a plurality of bifacial NAND memory devices The bifacial semiconductor wafer 200 may be used in a memory device such as, for example, a 3D NAND memory device [Shi para 0031] disposed over the interposer the semiconductor wafer 100 may include one or more through silicon vias 130 [Shi para 0030] each of the plurality of bifacial NAND memory devices and a plurality of bifacial NAND memory devices disposed over the interposer multiple bifacial semiconductor wafers may be stacked on top of each other to create, for example, a high capacity memory device [Shi para 0022] including: a first NAND memory die disposed on a first planar surface each semiconductor die on the first planar surface 220 to other semiconductor dies on the first planar surface 220. [Shi para 0034]; a second NAND memory die disposed on a second planar surface, opposite the first NAND memory die, the second planar surface positioned adjacent the interposer the second planar surface 240 may include multiple circuit layers (e.g., second circuit layer 260) or an array of semiconductor dies. [Shi para 0035] and a plurality of through silicon vias (TSVs) electrically coupling the first NAND memory die on the first planar surface with: the semiconductor wafer 100 may include one or more through silicon vias 130 that mechanically and/or electrically connect the individual semiconductor wafers together. [Shi para 0030] ; the second NAND memory die on the second planar surface, and the plurality of MUX. As shown in FIG. 2, the first planar surface 220 may include multiple circuit layers or an array of semiconductor dies. In an example, the semiconductor dies may be memory dies. [Shi para 0033]
Park discloses memory devices, and more particularly, to a buffer die capable of transmitting and/or receiving data at a relatively high speed and with reduced power consumption, and a stacked memory device including the same. Further Park discloses a buffer die provided in a wafer includes a write strobe signal generation circuit configured to, based on being enabled in a wafer level test on the buffer die, generate a first write strobe signal and a second write strobe signal having a phase difference of 180 degrees, a dividing and converting circuit configured to generate a plurality of divided clock signals having a phase difference of 90 degrees, a duty cycle adjusting circuit configured to generate a plurality of adjusted clock signals, a read strobe signal generation circuit configured to generate a first read strobe signal and a second read strobe signal having a phase difference of 180 degrees, a skew monitoring circuit configured to generate a first up/down signal, a trimming circuit is configured to generate a second up/down signal, generate a plurality of control code sets, and obtain a fuse calibration code.
Shi discloses a semiconductor device having one or more bifacial semiconductor wafers. The bifacial semiconductor wafer includes a first array of semiconductor dies on a first planar surface and a second array of semiconductor dies on a second planar surface that is opposite the first planar surface. The first array of semiconductor dies are electrically coupled via a first redistribution layer and the second array of semiconductor dies are electrically coupled via a second redistribution layer. One or more through silicon vias electrically couple the first array of semiconductor dies with the second array of semiconductor dies
Prior to the effective date of the invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Park and Shi in the art of manufacturing stacked memory devices and operating the same, as one of ordinary skill in the art would have recognized that the results of the combination were predictable as the combined teachings and technologies were well known in the art. Shi improves Park’s systems, methods and/or apparatus by increasing the storage capacity of a memory device while maintaining or reducing the size of the memory device distinct
during manufacturing.
Regarding claim 2 Park and Shi teaches claim 1 in addition Shi teaches wherein the plurality of bifacial NAND memory devices include: a first bifacial NAND memory device disposed directly over the interposer, the bifacial semiconductor wafer 200 may also include one or more through silicon vias 280. The through silicon vias 280 may extend from the first circuit layer 240, through the base layer 210, to the second circuit layer 260. [ Shi para 0037 and See Shi Fig. Two and Three] wherein the plurality of TSVs of the first bifacial NAND memory device include: a first plurality of TSVs extending through the first NAND memory die of the first bifacial NAND memory device; and a second plurality of TSVs extending through the second NAND memory die of the first bifacial NAND memory device, the bifacial semiconductor wafer includes … One or more through silicon vias (TSVs) facilitate signal transmission between the semiconductor dies on the first planar surface and the semiconductor dies on the second planar surface. [Shi para 0025] the second plurality of TSVs electrically coupled to: the first NAND memory die via the first plurality of TSVs, and the plurality of MUX; and at least one distinct bifacial NAND memory device disposed directly over the first bifacial NAND memory device, A second circuit layer is provided on the second planar surface. The second circuit layer may comprise a semiconductor die (e.g., memory die). Like the first planar surface, the second planar surface of the bifacial semiconductor wafer may include a series or an array of semiconductor dies. The second circuit layer also includes or is otherwise associated with a redistribution layer (RDL). The redistribution layer enables communication between the various semiconductor dies on the second planar surface. One or more through silicon vias (TSVs) facilitate signal transmission between the semiconductor dies on the first planar surface and the semiconductor dies on the second planar surface. [Shi para 0025] wherein the plurality of TSVs of the at least one distinct bifacial NAND memory device includes: a first distinct plurality of TSVs extending through the first NAND memory die of the at least one distinct bifacial NAND memory device; and a second distinct plurality of TSVs extending through the second NAND memory die of the at least one distinct bifacial NAND memory device, the second distinct plurality of TSVs electrically coupled a second planar surface (and/or one or more semiconductor dies on the second planar surface) of one bifacial semiconductor wafer is electrically coupled to a first planar surface (and/or one or more semiconductor dies on the first planar surface) of another bifacial semiconductor wafer. For example, the second planar surface 480 of the first bifacial semiconductor wafer 410 may be electrically coupled to a first planar surface 490 of the second bifacial semiconductor wafer 420. [Shi para 0045] to: the first distinct plurality of TSVs of the NAND memory die of the at least one distinct bifacial NAND memory device, and the first plurality of TSVs extending through the first NAND memory die of the first bifacial NAND memory device. a three dimensional (3D) NAND memory device. As shown in FIG. 1, the semiconductor wafer 100 includes a single circuit layer 110 provided on a base layer 120. In an example, the circuit layer 110 may comprise a semiconductor die. As briefly described above, in a traditional 3D NAND memory device, multiple semiconductor wafers 100 may be stacked on top of each other. In some examples, the semiconductor wafer 100 may include one or more through silicon vias 130 that mechanically and/or electrically connect the individual semiconductor wafers together. [Shi para 0030]
Regarding claim 3 Park and Shi teaches claim 2 in addition Shi teaches wherein the second plurality of TSVs of the first bifacial NAND memory device is electrically coupled to the plurality of MUX by way of one of: one or more solder bumps, or a hybrid wafer-to-wafer bond. solder bumps may be used to electrically couple or otherwise bond adjacent surfaces or faces of the bifacial semiconductor wafers to each other. [Shi para 0047] the first bifacial semiconductor wafer and the second bifacial semiconductor wafer may be coupled or otherwise bonded together by various wafer to wafer bonding processes including, but not limited to, copper to copper bonding and/or via one or more solder bumps/balls. [Shi para 0026]
Regarding claim 4 Park and Shi teaches claim 2 in addition Shi teaches wherein the second distinct plurality of TSVs of the at least one bifacial NAND memory device is electrically coupled to the first plurality of TSVs extending through the first NAND memory die of the first bifacial NAND memory device by one of: one or more solder bumps, or a hybrid wafer-to-wafer bond. solder bumps may be used to electrically couple or otherwise bond adjacent surfaces or faces of the bifacial semiconductor wafers to each other. [Shi para 0047] the first bifacial semiconductor wafer and the second bifacial semiconductor wafer may be coupled or otherwise bonded together by various wafer to wafer bonding processes including, but not limited to, copper to copper bonding and/or via one or more solder bumps/balls. [Shi para 0026]
Regarding claim 5 Park and Shi teaches claim 1 in addition Park teaches further comprising a controller electrically coupled to the plurality of MUX the delay controller 280 may include a first multiplexer 281, a second multiplexer 282, a third multiplexer 283, a fourth multiplexer 284 [Park para 0136] and the plurality of bifacial NAND memory devices disposed over the interposer. The interposer 1300 may connect the stacked memory device 1100 and the SoC 1200. The interposer 1300 may connect the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the SoC 1200 and may provide physical paths formed by using conductive materials. As such, the stacked memory device 1100 and the SoC 1200 may be stacked on the interposer 1300 [Park para 0223]
Regarding claim 6 Park and Shi teaches claim 5 in addition Park teaches wherein the controller is one of: positioned within a recess formed in the interposer, adjacent the plurality of MUX, or disposed on the interposer, opposite the plurality of bifacial NAND memory devices disposed over the interposer. The interposer 1300 may connect the stacked memory device 1100 and the SoC 1200. The interposer 1300 may connect the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the SoC 1200 and may provide physical paths formed by using conductive materials. As such, the stacked memory device 1100 and the SoC 1200 may be stacked on the interposer 1300 [Park para 0223]
Regarding claim 7 Park and Shi teaches claim 5 in addition Park teaches wherein the controller is disposed over the plurality of bifacial NAND memory device, opposite the interposer. The interposer 1300 may connect the stacked memory device 1100 and the SoC 1200. The interposer 1300 may connect the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the SoC 1200 and may provide physical paths formed by using conductive materials. As such, the stacked memory device 1100 and the SoC 1200 may be stacked on the interposer 1300 [Park para 0223]
Regarding claim 9 Park teaches an electronic device, comprising: a printed circuit board (PCB) For example, the package substrate 1400 may be a printed circuit board (PCB). [Park para 0224]; and at least one semiconductor package positioned on and electrically coupled to the PCB, the at least one semiconductor package a semiconductor package, [Park para 0216] including: an interposer The interposer 1300 may connect the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the SoC 1200 and may provide physical paths formed by using conductive materials [Park para 0223] disposed directly over and electrically coupled to the PCB, the interposer including a plurality of multiplexers (MUX) integrally formed within the interposer a semiconductor package 1000 may include a stacked memory device 1100, a system on a chip (SoC) 1200, an interposer 1300, and a package substrate 1400. The stacked memory device 1100 may include a buffer die 1110 and a plurality of core dies (e.g., a first core die 1120, a second core die 1130, a third core die 1140, and a fourth core die 1150). [Park Para 0216];; and
Park does not explicitly teach but Shi teaches a plurality of bifacial NAND memory devices The bifacial semiconductor wafer 200 may be used in a memory device such as, for example, a 3D NAND memory device [Shi para 0031] disposed over the interposer the semiconductor wafer 100 may include one or more through silicon vias 130 [Shi para 0030] and electrically coupled to the plurality of MUX and the PCB, each of the plurality of bifacial NAND memory device multiple bifacial semiconductor wafers may be stacked on top of each other to create, for example, a high capacity memory device [Shi para 0022] including: a first NAND memory die disposed on a first planar surface each semiconductor die on the first planar surface 220 to other semiconductor dies on the first planar surface 220. [Shi para 0034]; a second NAND memory die disposed on a second planar surface, opposite the first NAND memory die, the second planar surface positioned adjacent the interposer the second planar surface 240 may include multiple circuit layers (e.g., second circuit layer 260) or an array of semiconductor dies. [Shi para 0035]; and a plurality of through silicon vias (TSVs) One or more through silicon vias (TSVs) facilitate signal transmission between the semiconductor dies on the first planar surface and the semiconductor dies on the second planar surface. [Shi para 0035] electrically coupling the first NAND memory die on the first planar surface with: the second NAND memory die on the second planar surface, and the plurality of MUX. As shown in FIG. 2, the first planar surface 220 may include multiple circuit layers or an array of semiconductor dies. In an example, the semiconductor dies may be memory dies. [Shi para 0033]
Park discloses memory devices, and more particularly, to a buffer die capable of transmitting and/or receiving data at a relatively high speed and with reduced power consumption, and a stacked memory device including the same. Further Park discloses a buffer die provided in a wafer includes a write strobe signal generation circuit configured to, based on being enabled in a wafer level test on the buffer die, generate a first write strobe signal and a second write strobe signal having a phase difference of 180 degrees, a dividing and converting circuit configured to generate a plurality of divided clock signals having a phase difference of 90 degrees, a duty cycle adjusting circuit configured to generate a plurality of adjusted clock signals, a read strobe signal generation circuit configured to generate a first read strobe signal and a second read strobe signal having a phase difference of 180 degrees, a skew monitoring circuit configured to generate a first up/down signal, a trimming circuit is configured to generate a second up/down signal, generate a plurality of control code sets, and obtain a fuse calibration code.
Shi discloses a semiconductor device having one or more bifacial semiconductor wafers. The bifacial semiconductor wafer includes a first array of semiconductor dies on a first planar surface and a second array of semiconductor dies on a second planar surface that is opposite the first planar surface. The first array of semiconductor dies are electrically coupled via a first redistribution layer and the second array of semiconductor dies are electrically coupled via a second redistribution layer. One or more through silicon vias electrically couple the first array of semiconductor dies with the second array of semiconductor dies
Prior to the effective date of the invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Park and Shi in the art of manufacturing stacked memory devices and operating the same, as one of ordinary skill in the art would have recognized that the results of the combination were predictable as the combined teachings and technologies were well known in the art. Shi improves Park’s systems, methods and/or apparatus by increasing the storage capacity of a memory device while maintaining or reducing the size of the memory device distinct
during manufacturing.
Regarding claim 10 Park and Shi teaches claim 9 in addition Shi teaches wherein the plurality of bifacial NAND memory devices of the at least one semiconductor package include: a first bifacial NAND memory device disposed directly over the interposer, the bifacial semiconductor wafer 200 may also include one or more through silicon vias 280. The through silicon vias 280 may extend from the first circuit layer 240, through the base layer 210, to the second circuit layer 260. [ Shi para 0037 and See Shi Fig. Two and Three] wherein the plurality of TSVs of the first bifacial NAND memory device include: a first plurality of TSVs extending through the first NAND memory die of the first bifacial NAND memory device the bifacial semiconductor wafer includes … One or more through silicon vias (TSVs) facilitate signal transmission between the semiconductor dies on the first planar surface and the semiconductor dies on the second planar surface. [Shi para 0025]; and a second plurality of TSVs extending through the second NAND memory die of the first bifacial NAND memory device, the second plurality of TSVs electrically coupled to: the first NAND memory die via the first plurality of TSVs, and the plurality of MUX A second circuit layer is provided on the second planar surface. The second circuit layer may comprise a semiconductor die (e.g., memory die). Like the first planar surface, the second planar surface of the bifacial semiconductor wafer may include a series or an array of semiconductor dies. The second circuit layer also includes or is otherwise associated with a redistribution layer (RDL). The redistribution layer enables communication between the various semiconductor dies on the second planar surface. One or more through silicon vias (TSVs) facilitate signal transmission between the semiconductor dies on the first planar surface and the semiconductor dies on the second planar surface. [Shi para 0025]; and at least one distinct bifacial NAND memory device disposed directly over the first bifacial NAND memory device, wherein the plurality of TSVs of the at least one distinct bifacial NAND memory device a second planar surface (and/or one or more semiconductor dies on the second planar surface) of one bifacial semiconductor wafer is electrically coupled to a first planar surface (and/or one or more semiconductor dies on the first planar surface) of another bifacial semiconductor wafer. For example, the second planar surface 480 of the first bifacial semiconductor wafer 410 may be electrically coupled to a first planar surface 490 of the second bifacial semiconductor wafer 420. [Shi para 0045] includes: a first distinct plurality of TSVs extending through the first NAND memory die of the at least one distinct bifacial NAND memory device; and a second distinct plurality of TSVs extending through the second NAND memory die of the at least one distinct bifacial NAND memory device, the second distinct plurality of TSVs electrically coupled to: the first distinct plurality of TSVs of the NAND memory die of the at least one distinct bifacial NAND memory device, and the first plurality of TSVs extending through the first NAND memory die of the first bifacial NAND memory device. a three dimensional (3D) NAND memory device. As shown in FIG. 1, the semiconductor wafer 100 includes a single circuit layer 110 provided on a base layer 120. In an example, the circuit layer 110 may comprise a semiconductor die. As briefly described above, in a traditional 3D NAND memory device, multiple semiconductor wafers 100 may be stacked on top of each other. In some examples, the semiconductor wafer 100 may include one or more through silicon vias 130 that mechanically and/or electrically connect the individual semiconductor wafers together. [Shi para 0030]
Regarding claim 11 Park and Shi teaches claim 10 in addition Shi teaches wherein the second plurality of TSVs of the first bifacial NAND memory device is electrically coupled to the plurality of MUX by way of one of: one or more solder bumps, or a hybrid wafer-to-wafer bond. solder bumps may be used to electrically couple or otherwise bond adjacent surfaces or faces of the bifacial semiconductor wafers to each other. [Shi para 0047] the first bifacial semiconductor wafer and the second bifacial semiconductor wafer may be coupled or otherwise bonded together by various wafer to wafer bonding processes including, but not limited to, copper to copper bonding and/or via one or more solder bumps/balls. [Shi para 0026]
Regarding claim 12 Park and Shi teaches claim 10 in addition Shi teaches wherein the second distinct plurality of TSVs of the at least one bifacial NAND memory device is electrically coupled to the first plurality of TSVs extending through the first NAND memory die of the first bifacial NAND memory device by one of: one or more solder bumps, or a hybrid wafer-to-wafer bond. solder bumps may be used to electrically couple or otherwise bond adjacent surfaces or faces of the bifacial semiconductor wafers to each other. [Shi para 0047] the first bifacial semiconductor wafer and the second bifacial semiconductor wafer may be coupled or otherwise bonded together by various wafer to wafer bonding processes including, but not limited to, copper to copper bonding and/or via one or more solder bumps/balls. [Shi para 0026]
Regarding claim 13 Park and Shi teaches claim 9 in addition Park teaches, wherein the at least one semiconductor package further includes a controller electrically coupled to the plurality of MUX formed integrally within the interposer the delay controller 280 may include a first multiplexer 281, a second multiplexer 282, a third multiplexer 283, a fourth multiplexer 284 [Park para 0136] and the plurality of bifacial NAND memory devices disposed over the interposer. The interposer 1300 may connect the stacked memory device 1100 and the SoC 1200. The interposer 1300 may connect the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the SoC 1200 and may provide physical paths formed by using conductive materials. As such, the stacked memory device 1100 and the SoC 1200 may be stacked on the interposer 1300 [Park para 0223]
Regarding claim 14 Park and Shi teaches claim 13 in addition Park teaches wherein the controller is one of: positioned within a recess formed in the interposer, adjacent the plurality of MUX, or disposed on the interposer, opposite the plurality of bifacial NAND memory devices disposed over the interposer. The interposer 1300 may connect the stacked memory device 1100 and the SoC 1200. The interposer 1300 may connect the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the SoC 1200 and may provide physical paths formed by using conductive materials. As such, the stacked memory device 1100 and the SoC 1200 may be stacked on the interposer 1300 [Park para 0223]
Regarding claim 15 Park and Shi teaches claim 13 in addition Park teaches, wherein the controller is disposed over the plurality of bifacial NAND memory device, opposite the interposer. The interposer 1300 may connect the stacked memory device 1100 and the SoC 1200. The interposer 1300 may connect the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the SoC 1200 and may provide physical paths formed by using conductive materials. As such, the stacked memory device 1100 and the SoC 1200 may be stacked on the interposer 1300 [Park para 0223]
Regarding claim 17 Park and Shi teaches claim 9 in addition Park teaches wherein the interposer of the at least one semiconductor package is electrically coupled to PCB by one or more solder bumps. The semiconductor package 1000 may exchange signals with another external package or semiconductor devices through the solder balls 1104. For example, the package substrate 1400 may be a printed circuit board (PCB). [Park para 0224]
Regarding claim 18 Park teaches a semiconductor package, a semiconductor package, [Park para 0216] comprising: an interposer The interposer 1300 may connect the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the SoC 1200 and may provide physical paths formed by using conductive materials [Park para 0223] including a plurality of multiplexers (MUX) integrally formed within the interposer a semiconductor package 1000 may include a stacked memory device 1100, a system on a chip (SoC) 1200, an interposer 1300, and a package substrate 1400. The stacked memory device 1100 may include a buffer die 1110 and a plurality of core dies (e.g., a first core die 1120, a second core die 1130, a third core die 1140, and a fourth core die 1150). [Park Para 0216];
Park does not explicitly teach but Shi discloses and a plurality of bifacial NAND memory devices The bifacial semiconductor wafer 200 may be used in a memory device such as, for example, a 3D NAND memory device [Shi para 0031] disposed over the interposer the semiconductor wafer 100 may include one or more through silicon vias 130 [Shi para 0030], each of the plurality of bifacial NAND memory device multiple bifacial semiconductor wafers may be stacked on top of each other to create, for example, a high capacity memory device [Shi para 0022] including: a first NAND memory die disposed on a first planar surface each semiconductor die on the first planar surface 220 to other semiconductor dies on the first planar surface 220. [Shi para 0034]; a second NAND memory die disposed on a second planar surface, opposite the first NAND memory die, the second planar surface positioned adjacent the interposer the second planar surface 240 may include multiple circuit layers (e.g., second circuit layer 260) or an array of semiconductor dies. [Shi para 0035] the semiconductor wafer 100 may include one or more through silicon vias 130 that mechanically and/or electrically connect the individual semiconductor wafers together. [Shi para 0030]; and means for electrically coupling the first NAND memory die on the first planar surface with: the second NAND memory die on the second planar surface, and the plurality of MUX. As shown in FIG. 2, the first planar surface 220 may include multiple circuit layers or an array of semiconductor dies. In an example, the semiconductor dies may be memory dies. [Shi para 0033];
Park discloses memory devices, and more particularly, to a buffer die capable of transmitting and/or receiving data at a relatively high speed and with reduced power consumption, and a stacked memory device including the same. Further Park discloses a buffer die provided in a wafer includes a write strobe signal generation circuit configured to, based on being enabled in a wafer level test on the buffer die, generate a first write strobe signal and a second write strobe signal having a phase difference of 180 degrees, a dividing and converting circuit configured to generate a plurality of divided clock signals having a phase difference of 90 degrees, a duty cycle adjusting circuit configured to generate a plurality of adjusted clock signals, a read strobe signal generation circuit configured to generate a first read strobe signal and a second read strobe signal having a phase difference of 180 degrees, a skew monitoring circuit configured to generate a first up/down signal, a trimming circuit is configured to generate a second up/down signal, generate a plurality of control code sets, and obtain a fuse calibration code.
Shi discloses a semiconductor device having one or more bifacial semiconductor wafers. The bifacial semiconductor wafer includes a first array of semiconductor dies on a first planar surface and a second array of semiconductor dies on a second planar surface that is opposite the first planar surface. The first array of semiconductor dies are electrically coupled via a first redistribution layer and the second array of semiconductor dies are electrically coupled via a second redistribution layer. One or more through silicon vias electrically couple the first array of semiconductor dies with the second array of semiconductor dies
Prior to the effective date of the invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Park and Shi in the art of manufacturing stacked memory devices and operating the same, as one of ordinary skill in the art would have recognized that the results of the combination were predictable as the combined teachings and technologies were well known in the art. Shi improves Park’s systems, methods and/or apparatus by increasing the storage capacity of a memory device while maintaining or reducing the size of the memory device distinct
during manufacturing.
Regarding claim 19 Park and Shi teaches claim 18 in addition Shi wherein the plurality of bifacial NAND memory devices include: a first bifacial NAND memory device disposed directly over the interposer the bifacial semiconductor wafer 200 may also include one or more through silicon vias 280. The through silicon vias 280 may extend from the first circuit layer 240, through the base layer 210, to the second circuit layer 260. [ Shi para 0037 and See Shi Fig. Two and Three] and including: a first means for electrically coupling the first NAND memory die of the first bifacial NAND memory device to the second NAND memory die of the first bifacial NAND memory device the bifacial semiconductor wafer includes … One or more through silicon vias (TSVs) facilitate signal transmission between the semiconductor dies on the first planar surface and the semiconductor dies on the second planar surface. [Shi para 0025]; and a second means for electrically coupling the second NAND memory die of the first bifacial NAND memory device to the plurality of MUX; and at least one distinct bifacial NAND memory device disposed directly over the first bifacial NAND memory device, the at least one distinct bifacial NAND memory device A second circuit layer is provided on the second planar surface. The second circuit layer may comprise a semiconductor die (e.g., memory die). Like the first planar surface, the second planar surface of the bifacial semiconductor wafer may include a series or an array of semiconductor dies. The second circuit layer also includes or is otherwise associated with a redistribution layer (RDL). The redistribution layer enables communication between the various semiconductor dies on the second planar surface. One or more through silicon vias (TSVs) facilitate signal transmission between the semiconductor dies on the first planar surface and the semiconductor dies on the second planar surface. [Shi para 0025] including: a first means for electrically coupling the first NAND memory die of the at least one distinct bifacial NAND memory device to the second NAND memory die of the at least one distinct bifacial NAND memory device a second planar surface (and/or one or more semiconductor dies on the second planar surface) of one bifacial semiconductor wafer is electrically coupled to a first planar surface (and/or one or more semiconductor dies on the first planar surface) of another bifacial semiconductor wafer. For example, the second planar surface 480 of the first bifacial semiconductor wafer 410 may be electrically coupled to a first planar surface 490 of the second bifacial semiconductor wafer 420. [Shi para 0045]; and a second means for electrically coupling the second NAND memory die of the at least one distinct bifacial NAND memory device to the first NAND memory die of the first bifacial NAND memory device. a three dimensional (3D) NAND memory device. As shown in FIG. 1, the semiconductor wafer 100 includes a single circuit layer 110 provided on a base layer 120. In an example, the circuit layer 110 may comprise a semiconductor die. As briefly described above, in a traditional 3D NAND memory device, multiple semiconductor wafers 100 may be stacked on top of each other. In some examples, the semiconductor wafer 100 may include one or more through silicon vias 130 that mechanically and/or electrically connect the individual semiconductor wafers together. [Shi para 0030]
Regarding claim 20 Park and Shi teaches claim 18 in addition Park further comprising a controller including means for electrically coupling the controller to the plurality of MUX and the plurality of bifacial NAND memory devices disposed over the interposer. The interposer 1300 may connect the stacked memory device 1100 and the SoC 1200. The interposer 1300 may connect the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the SoC 1200 and may provide physical paths formed by using conductive materials. As such, the stacked memory device 1100 and the SoC 1200 may be stacked on the interposer 1300 [Park para 0223]
Conclusion
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/ROBERT J MICHAUD/Examiner, Art Unit 2622
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