Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application has been examined. Claims 2-21 are pending. Claim 1 is cancelling.
The Group and/or Art Unit location of your application in the PTO has changed. To aid in correlating any papers for this application, all further correspondence regarding this application should be directed to Group Art Unit 2175.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
4. The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
5. Claims 2, 3, 5, 7, 9, 18, 19, 21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 5, 11, 8, 17, 18, 21 respectively of U.S. Patent No. 12,072,767. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1, 2, 5, 11, 8, 17, 18, 21 of the US Patent No. 12,072,767 are similar in scope to claims 2, 3, 5, 7, 9, 18, 19, 21 of the present application with only obvious wording variations
Present Application
Pat No. 12,072,767
2. A memory system, comprising:
one or more memory devices; and one or more
controllers coupled with the one or more memory devices, wherein the one or more controllers are configured to cause the memory system to:
detect an error associated with a boot-up procedure of the memory system;
store error information associated the error in a persistent register of the memory system; and
reset the memory system in accordance with storing the error information in the persistent register of the memory system.
3. The memory system of claim 2, wherein the one or more controllers are further configured to cause the memory system to: execute a second boot-up procedure of the memory system in accordance with resetting the memory system; and
transfer the error information from the persistent register to a non-volatile memory device in accordance with executing the second boot-up procedure.
5. The memory system of claim 2, wherein the one or more controllers are further configured to cause the memory system to: initialize a bootloader of the memory system; and perform the boot-up procedure of the memory system in accordance with initializing the bootloader of the memory system, wherein detecting the error is in accordance with performing the boot-up procedure.
7. The memory system of claim 5, wherein the one or more controllers are further configured to cause the memory system to: switch, in accordance with initializing the bootloader of the memory system, from a first power mode associated with a first power consumption to a second power mode associated with a second power consumption, wherein detecting the error is in accordance with the switching.
9. The memory system of claim 2, wherein the persistent register maintains a value stored in the persistent register throughout the reset of the memory system, wherein the one or more controllers are further configured to cause the memory system to: transfer the error information from the persistent register to a non-volatile memory device in accordance with the persistent register maintaining the value stored in the persistent register throughout resetting the memory system.
18. A non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of a memory system, cause the memory system to:
detect an error associated with a boot-up procedure of the memory system;
store error information associated the error in a persistent register of the memory system; and
reset the memory system in accordance with storing the error information in the persistent register of the memory system.
19. The non-transitory computer-readable medium of claim 18, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: execute a second boot-up procedure of the memory system in accordance with resetting the memory system; and transfer the error information from the persistent register to a non-volatile memory device in accordance with executing the second boot-up procedure.
21. The non-transitory computer-readable medium of claim 18, wherein the instructions, when executed by the one or more processors of the memory system, further cause the memory system to: initialize a bootloader of the memory system; and perform the boot-up procedure of the memory system in accordance with initializing the bootloader of the memory system, wherein detecting the error is in accordance with performing the boot-up procedure.
1. An apparatus, comprising:
a read-only memory device; a non-volatile memory device; a persistent register; and a
controller coupled with the read-only memory device, the non-volatile memory device, and the persistent register, wherein the controller is configured to cause the apparatus to:
store, in the persistent register, error information associated with performing the boot-up procedure of the apparatus based at least in part on detecting the error;
reset the apparatus based at least in part on storing the error information and detecting the error; and transfer the error information from the persistent register to the non-volatile memory device based at least in part on resetting the apparatus.
2. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: execute a second boot-up procedure of a bootloader of the apparatus based at least in part on resetting the apparatus; and
transfer, from the persistent register to a cache and based at least in part on executing the second boot-up procedure of the bootloader, the error information associated, wherein transferring the error information to the non-volatile memory device is based at least in part on transferring the error information to the cache.
5. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to: initialize a bootloader of the apparatus based at least in part on initializing the read-only memory device and performing the boot-up procedure of the apparatus, wherein detecting the error is based at least in part on initializing the bootloader;
11. The apparatus of claim 5, wherein the controller is further configured to cause the apparatus to: switch, base at least in part on initializing the bootloader of the apparatus, from a first power mode associated with a first power consumption to a second power mode associated with a second power consumption, wherein detecting the error is based at least in part on the switching.
8. The apparatus of claim 1, wherein: the persistent register maintains a value stored in the persistent register throughout a resetting of the apparatus; and transferring the error information from the persistent register to the non-volatile memory device is based at least in part on the persistent register maintaining the value stored in the persistent register throughout resetting the apparatus.
17. A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to:
detect, based at least in part on initializing the read-only memory device, an error associated with performing the boot-up procedure of the electronic device;
store, in a persistent register at the electronic device, error information associated with performing the boot-up procedure of the electronic device based at least in part on detecting the error; reset the electronic device based at least in part on storing the error information and detecting the error; and transfer the error information from the persistent register to a non-volatile memory device at the electronic device based at least in part on resetting the electronic device.
18. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: execute a second boot-up procedure of a bootloader of the electronic device based at least in part on resetting the electronic device; and transfer, from the persistent register of the electronic device to a cache and based at least in part on executing the second boot-up procedure of the bootloader,
21. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: initialize a bootloader of the electronic device based at least in part on initializing the read-only memory device and performing the boot-up procedure of the electronic device, wherein detecting the error is based at least in part on initializing the bootloader;
In re Karlson, 136 USPQ 189 (ccPA 1963).
Claim Objection
Claims 2 and 18 are objected to because of the following informalities/grammatical error.
Claim 2:
“…store error information associated with the error in a persistent register…”
Claim 18:
“…store error information associated with the error in a persistent register…”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 2, 5, 18, 21 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Krithivas et al. (US Pub No. 2019/0042348) in view of Michihata et al. (EP No. 2733612A1).
In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art.
The examiner relies on the entire teachings of Krithivas and Michihata references; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
In regard to claims 2, 18, Krithivas et al. disclose non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of a memory system (¶ 84, 86), a memory system, comprising: one or more memory devices (i.e. sticky registers items 225 of figure 2); and one or more controllers (item 102 of figure 1) coupled with the one or more memory devices, wherein the one or more controllers are configured to cause the memory system to: detect an error associated with a catastrophic failure of the system; store error information associated with the error in a persistent register of the memory system (as shown in Fig. 2, which is reproduced below for ease of reference and convenience, Krithivas discloses the logic and/or features of management controller 102 may detect or sense that a catastrophic error has occurred in system 100. In some examples, a three-strike timeout catastrophic error may be signaled by components of package 101 such as CPU 110 via a CATERR/IERR signal. For these examples, IP blocks located at uncore 114, integrated CDs 120/130 and discrete CDs 140/150 may store error information in their respective registers to indicate state information of these IP blocks at the time of the three-strike timeout catastrophic error responsive to the CATERR/IERR signal. See ¶ 30-31, 40-41);
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wherein the one or more controllers are configured to cause the memory system to: detect an error (in Krithivas, logic and/or features of management controller 102 may detect or sense that a catastrophic error has occurred in system 100. In some examples, a three-strike timeout catastrophic error may be signaled by components of package 101 such as CPU 110 via a CATERR/IERR signal. For these examples, IP blocks located at uncore 114, integrated CDs 120/130 and discrete CDs 140/150 may store error information in their respective registers to indicate state information of these IP blocks at the time of the three-strike timeout catastrophic error responsive to the CATERR/IERR signal. See ¶ 40-41); store error information associated the error in a persistent register of the memory system (in Krithivas, the IP blk(s) 155-2 may cause error information indicating respective state information at the time of the three-strike timeout catastrophic error to be stored to respective registers 255-1 and 255-2. See ¶ 47, 49, 55); and reset the memory system in accordance with storing the error information in the persistent register of the memory system (in Krithivas, the registers 225-3, 225-4, 235-1, 235-2, 255-1 or 255-2 may be sticky registers arranged to preserve stored information or data following warm resets of system 100 to enable primary PECI 111, secondary PECI 105-2 or secondary PECI 105-4 to provide error information included in the crash information or data to management controller 102 responsive to receiving PECI commands from management controller 102. In other words, registers 225-3, 225-4, 235-1, 235-2, 255-1 or 255-2 do not revert or reset to default values following a warm reset to allow primary PECI 111, secondary PECI 105-2 or secondary PECI 105-4 to retrieve error information from these registers after the warm reset. See ¶ 30). But Krithivas et al. do not disclose the detection of error associated with a boot-up procedure of the memory. In the same field of endeavor, Michihata et al. teach that the memory stores boot program data, backup program data, and corrective data. During system booting, if faults are detected (bit error), memory stores error detection data for detecting bit errors in the boot program data (as shown in Fig. 2, which is reproduced below for ease of reference and convenience, Michihata discloses the boot program data are executed to boot a system. If faults are detected in the boot program, the memory 2 stores error detection data for detecting bit errors in the boot program data. See ¶ 13-14). It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Krithivas to store the error data during booting, as taught by Michihata et al., in order to enable the faster booting and prevent system hang.
In regard to claims 5, 21, Michihata et al. disclose wherein the one or more controllers are further configured to cause the memory system to: initialize a bootloader of the memory system (in Michihata, the boot program data are executed to boot a system. If faults are detected in the boot program, the memory 2 stores error detection data for detecting bit errors in the boot program data. See ¶ 13-14); and perform the boot-up procedure of the memory system in accordance with initializing the bootloader of the memory system, wherein detecting the error is in accordance with performing the boot-up procedure (in Michihata discloses the boot program data are executed to boot a system. If faults are detected in the boot program, the memory 2 stores error detection data for detecting bit errors in the boot program data. See ¶ 13-14).
In regard to claim 6, Michihata et al. wherein: the error is associated with initializing the bootloader of the memory system; and the error information is associated with initializing the bootloader of the memory system (in Michihata discloses the boot program data are executed to boot a system. If faults are detected in the boot program, the memory 2 stores error detection data for detecting bit errors in the boot program data. See ¶ 13-14).
In regard to claim 9, Krithivas et al. wherein the persistent register maintains a value stored in the persistent register throughout the reset of the memory system, wherein the one or more controllers are further configured to cause the memory system to: transfer the error information from the persistent register to a non-volatile memory device in accordance with the persistent register maintaining the value stored in the persistent register throughout resetting the memory system (in Krithivas, the registers 225-3, 225-4, 235-1, 235-2, 255-1 or 255-2 may be sticky registers arranged to preserve stored information or data following warm resets of system 100 to enable primary PECI 111, secondary PECI 105-2 or secondary PECI 105-4 to provide error information included in the crash information or data to management controller 102 responsive to receiving PECI commands from management controller 102. In other words, registers 225-3, 225-4, 235-1, 235-2, 255-1 or 255-2 do not revert or reset to default values following a warm reset to allow primary PECI 111, secondary PECI 105-2 or secondary PECI 105-4 to retrieve error information from these registers after the warm reset. See ¶ 30).
In regard to claim 10, Krithivas et al. wherein the error information comprises a first value corresponding to a real time counter (i.e. timeout) of the memory system, a second value stored by a hardware register of the memory system, firmware data associated with the memory system, or a combination thereof (in Krithivas, firmware components of the OOB-MSM (e.g., power control unit firmware) may fail due to the catastrophic error and other types of catastrophic errors may include, but are not limited to, a three-strike timeout. See ¶ 18, 30, 49).
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Allowable Subject Matter
7. Claims 11-17 are allowable over the prior of records.
8. Claims 3-4, 7-8, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an Examiner's statement of reasons for the indication of allowable subject matter: Claims 3, 7, 11, 19 are allowable over the prior art of record because the prior arts, cited in its entirety, or in combination, do not teach
wherein the one or more controllers are further configured to cause the memory system to: execute a second boot-up procedure of the memory system in accordance with resetting the memory system; and transfer the error information from the persistent register to a non-volatile memory device in accordance with executing the second boot-up procedure (claims 3, 19)
wherein the one or more controllers are further configured to cause the memory system to: switch, in accordance with initializing the bootloader of the memory system, from a first power mode associated with a first power consumption to a second power mode associated with a second power consumption, wherein detecting the error is in accordance with the switching (claim 7);
a memory system, comprising: one or more memory devices; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to: transfer the first error information from the persistent register to a cache of the memory system in accordance with a transfer of second error information from the cache to a non-volatile memory device (claim 11).
Conclusion
9. Claims 1-10, 18-21 are rejected. Claims 11-17 are allowed.
10. The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Padilla, Jr. et al. (US Pub No. 2019/0278653) disclose a system configured to determine that a trigger condition has occurred that is related to an operation performed on a memory device of the system. Responsive to determining that the trigger condition has occurred, reordering error handling mechanisms of an error handling sequence based upon an error handling mechanism performance metric. Each error handling mechanism specifies operations to be performed to recover an error in the operation on the memory device.
Gjorup (US Pub No. 2015/0280749) discloses the boot data includes executable boot code and corresponding error correction information. The computer processor hardware applies first error correction decoding to the retrieved boot data. In response to detecting an inability to decode the retrieved boot data via application of the first error correction decoding, the computer processor hardware applies second error correction decoding to the retrieved boot data to configure the computer processor hardware.
Raj et al. (US Pub No. 2015/0113334) disclose the system can include a machine check counter (MCC) including a current value. The current value indicates a system reboot resetting hardware of the computing system. The machine check counter includes a model specific register including a counter indicating the current value, the current value to be incremented upon the system reboot.
Abe et al. (US Pub No. 2008/0148038) disclose the first ROM image is initially selected to boot a data processing system utilizing a first basic input output system (BIOS) program. In response to determining that contents of the first ROM image and the second ROM image are different, the second ROM image is selected. The data processing system boots utilizing the second BIOS program stored by the second ROM image.
Mittal et al. (US Pub No. 2014/0223239) disclose memory error management system connected to memory channels for managing errors detected in corresponding memory devices includes a reporting table including a list of historically reported errors, a binary value representing the current error status of the memory channels, a uniqueness check module for checking whether a historically reported error is reappearing as a current error.
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
Communications via Internet e-mail regarding this application, other than those under 35 U.S.C. 132 or which otherwise require a signature, may be used by the applicant and should be addressed to [raymond.phan@uspto.gov].
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 central telephone number is (571) 272-2100.
/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175