DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-2, 9-10, 15-16, and 18-19) in the reply filed on 9/29/2026 is acknowledged. Election is made final.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 9-10, 15-16, and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho (20230207414).
In re claim 1, Cho teaches a semiconductor packaging structure (Fig. 5), comprising: a first packaging body (lower part of the structure) comprising a first substrate (roughly corresponding to 110) and a first chip (roughly corresponding to 121; ¶0030 indicates the structure is a chip), said first chip located on the first substrate (fig. 5 shows this); and a second packaging body (roughly corresponding to 140) coupled to the first packaging body (Fig. 5 shows “coupling”), said second packaging body comprising a second substrate (Fig. 5 shows 140 is a substrate), the first chip being located between the first substrate and the second substrate (Fig. 5 shows 121 between 110 and 140); wherein a ratio of a thickness of the first chip T1 to a distance between the first substrate and the second substrate D1 is less than 0.5 - Fig. 5 shows that element 11 of 121 is less than half the space between 140 and 110. However, since it is not explicitly recited, it would also be obvious to optimize the distance as ¶0057 of Cho indicates that optimizing the thickness of the chips is known in the art. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to make the ratio of T1 to D1 be less than .5 as optimizing a result effective variable (Cho ¶0057 again shows it is acknowledge as a result effective variable) requires routine skill in the art. A motivation for doing so can be drawn from Cho ¶0057 indicating an optimization of heat generation and dissipation characteristics.
In re claim 2, Cho teaches The semiconductor packaging structure of claim 1, but does not explicitly teach wherein T1 is between 50 μm and 90 μm. It would have been obvious to one of ordinary skill in the art at the time the invention was made to make T1 be between 50 μm and 90 μm as optimizing a result effective variable (Cho ¶0057 again shows it is acknowledge as a result effective variable) requires routine skill in the art. A motivation for doing so can be drawn from Cho ¶0057 indicating an optimization of heat generation and dissipation characteristics.
In re claim 9, Cho teaches the semiconductor packaging structure of claim 1, wherein the first packaging body further comprises: an encapsulation layer filled between the first substrate and the second substrate, and wrapping around and encapsulating the first chip (Fig. 5 element 130, ¶0030 indicates it is an encapsulation layer); and a conductive structure located in the encapsulation layer, disposed at a periphery of the first chip, and electrically connecting the first substrate with the second substrate (Fig. 5 element 135 and ¶0033 teaches it electrically connects).
In re claim 10, Cho teaches the semiconductor packaging structure of claim 9, further comprising: a first wiring layer, disposed in the first substrate, and electrically connected with a first lower surface of the first chip (Fig. 5 shows wiring layers within 110 that are connected by the UBM to 121), the first lower surface being a surface of the first chip near the first substrate (Fig. 5 shows this); and a second wiring layer, disposed in the second substrate, and electrically connected with the first wiring structure via the conductive structure (Fig. 5 shows wiring layers in 140 and an electrical connection to the first wiring layer via 135).
In re claim 15, Cho teaches a semiconductor component, comprising a semiconductor packaging structure comprising: a first packaging body comprising a first substrate and a first chip located on the first substrate; and a second packaging body coupled to the first packaging body and comprising a second substrate, the first chip being located between the first substrate and the second substrate; wherein a ratio of a thickness of the first chip T1 to a distance between the first substrate and the second substrate D1 is less than 0.5 (this is rejected under the same logic as claim 1 as the limitations are the basically the same but for the “semiconductor component” part, and ¶0084 indicates the use of this packaging in semiconductor components).
In re claim 16, Cho teaches The semiconductor component of claim 15, wherein T1 is between 50 μm and 90 μm (this is rejected under the same logic as claim 2).
In re claim 18, Cho teaches An electronic device, comprising a semiconductor packaging structure, comprising: a first packaging body comprising a first substrate and a first chip located on the first substrate; and a second packaging body coupled to the first packaging body and comprising a second substrate, the first chip being located between the first substrate and the second substrate; wherein a ratio of a thickness of the first chip T1 to a distance between the first substrate and the second substrate D1 is less than 0.5. (this is rejected under the same logic as claim 1 as the limitations are the basically the same but for the “electronic device” part, and ¶0084 indicates the use of this packaging in electronic devices such as computer memory and EDP devices).
In re claim 19, Cho teaches The electronic device of claim 18, wherein T1 is between 50 μm and 90 μm (this is rejected under the same logic as claim 2).
Conclusion
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/DALE E PAGE/ Supervisory Patent Examiner, Art Unit 2899
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