Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed, approved immediately upon submission, and reduces waiting time for Terminal Disclaimer to be manually approved. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1, 15, and 19 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over Claims 1 and 2 of U.S. Patent No. 10,788,853, since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent. Although the conflicting claims are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is at least fully disclosed in the reference patent, as mapped below:
U.S. Application No. 18/804,364 Claims
U.S. Patent No. 10,788,853 Claims
1. A circuit, comprising:
a first flip-flop (106) including a first input and an output, wherein the first flip-flop is configured to: receive, at the first input, a first signal representing an interrupt request; and generate, at the output, a first output signal based on the first signal;
1. A circuit comprising: a first flip-flop (106) having a first input, a second input, and an output, the first input configured to receive an interrupt request signal (104) from a second circuit, the second input configured to receive a second clock signal from the second circuit;
*It is understood in the art of flip-flop circuits that the output is generated based on the signals received on the inputs of the flip flop*
a second flip-flop (116) including a first input and an output, wherein the second flip-flop is configured to: receive, at the first input, a second signal representing an acknowledgement of the interrupt request; and generate, at the output, a second output signal based on the second signal;
and a third flip-flop (116) having a first input, a second input, and an output, the first input of the third flip-flop configured to receive an acknowledge signal (130) from a first circuit, the second input of the third flip-flop configured to receive a first clock signal from the first circuit, and the output of the third flip-flop configured to provide an interrupt clear signal (113) to the second flip-flop in response to the acknowledgment signal from the first circuit.
and a third flip-flop (112) including a first input (numeral 111 of ‘853), a second input (see claim 2 of ‘853), and an output, the first input coupled to the output of the first flip-flop, and the second input coupled to the output of the second flip-flop (CLEAR signal 115), wherein the third flip-flop is configured to: generate, at the output, a third output signal based on the first output signal and the second output signal (output signal 118 based on signals 111 and 115).
a second flip-flop (112) having a clock input and an output, the clock input coupled to the output of the first flip-flop (set_flag 111) and the output of the second flip-flop configured to provide an interrupt input signal (118);
2. The circuit of claim 1, wherein the interrupt request signal has a first state indicating no interrupt is requested by the second circuit, and a second state indicating an interrupt is requested by the second circuit; wherein the interrupt clear signal has a first state and a second state; wherein the output of the second flip-flop is configured to: provide the interrupt input signal in a first state in response to a second input of the second flip-flop receiving the interrupt clear signal (115) in the first state; and provide the interrupt input signal in a second state in response to the interrupt request signal transitioning from the first state to the second state when the interrupt clear signal is in the second state; and wherein the third flip-flop is configured to provide the interrupt clear signal in the first state to reset the second flip-flop to set the interrupt input signal to the first state in response to the acknowledgment signal from the first circuit.
Claim 15 represents a method embodiment of the circuit of claim 1.
See above mapping with respect to claims 1 and 2 of ‘853.
17. The method of claim 15, further comprising: receiving, at a second input of the first flip-flop, a first clock signal;
and receiving, at a second input of the second flip-flop, a second clock signal.
1. A circuit comprising: a first flip-flop (106) having a first input, a second input, and an output, the first input configured to receive an interrupt request signal (104) from a second circuit, the second input configured to receive a second clock signal from the second circuit;
and a third flip-flop (116) having a first input, a second input,….. the second input of the third flip-flop configured to receive a first clock signal from the first circuit
18. The method of claim 17, wherein the second input of the first flip-flop is a clock input of the first flip-flop, and wherein the second input of the second flip-flop is a clock input of the second flip-flop.
See above with respect to claim 17 of ‘853 as Claim 18 of the instant application is merely stating that the inputs of the flip-flops that receive the clock signals of claim 17 are “clock inputs”.
19. The method of claim 17, wherein the first signal is generated according to the first clock signal, and the second signal is generated according to the second clock signal.
See above with respect to claims 1 and 2 of ‘853 as the flip flops are presented with an input, a clock input, and an output. Flip flops operate by saving the data present at the input and outputting the saved data, all according to the clock signal rising or falling edges.
Allowable Subject Matter
Claims 1-20 would be allowable in the event of a Terminal Disclaimer being filed and accepted to overcome the Double Patenting Rejection above.
The following is a statement of reasons for the indication of allowable subject matter:
Independent claims 1 and 15 map similarly to claim 1 of parent patent no. 10,788,853, with the claimed second flip-flop mapping to the third flip flop of patent ‘853 and the claimed third flip flop mapping to the second flip flop of patent ‘853. Several small changes are made to the instant independent claims (with some limitations be moved to dependent claims), such as: the first flip flop doesn’t comprise a second input receiving a second clock signal, the interrupt request isn’t received from a second circuit, and the second flip flop not receiving the acknowledgement from a first circuit.
Independent claims 1 and 15 are considered to distinguish over the prior art due to the specific combination and manner of the three flip flops being interconnected with their input and output signals, the interrupt request, and acknowledgement signals.
Claims 2-14 and 16-20 inherit the allowable subject matter of claims 1 and 15, respectively.
- Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889 - (Direct Fax: 571-273-0889). The examiner can normally be reached on M-F: 8-4:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached on (571) 272-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Brian T Misiura/
Primary Examiner, Art Unit 2175