Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d), However, none of the certified copies of the priority documents have been received.
Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 10, and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Grobis et al. (US 20210065791 A1).
Regarding claim 1: Grobis discloses a resistive memory device (FIG. 1G) performing a selective write operation (write process 600b, FIG. 6B), comprising: at least one memory cell (of memory arrays 174 and 176, FIG. 1G); a reference resistance circuit whose reference resistance value is adjusted (read reference, write reference, par. 97); a sense amplifier (read circuit 150, FIG. 1D; control circuits may include sense amplifier, par. 28) configured to read existing data stored in the at least one memory cell (read and determine state of memory cell, par. 37) by comparing a resistance value of the at least one memory cell with the reference resistance value of the reference resistance circuit (step 610a, FIG. 6A); a write driver (write circuit 150, FIG. 1D) configured to program write data into the at least one memory cell (write process 600b, FIG. 6B); and a selective write controller (100) configured to perform a read-before-write (read-before-write (RBW), par. 37) operation by adjusting the reference resistance value of the reference resistance circuit (adjust read and write parameters, par. 97) according to the write data during the selective write operation.
Regarding claim 10: Grobis discloses a writing method of a resistive memory device (FIG. 1G) performing a selective write operation (write process 600b, FIG. 6B), comprising: receiving write data to be written (receive write command 602b, FIG. 6B) into a selected memory cell (of memory arrays 174 and 176, FIG. 1G); increasing or decreasing a reference resistance (adjust read and write parameters, par. 97) for a read-before-write (read-before-write (RBW), par. 37) operation to the selected memory cell according to a value of the write data to obtain a changed reference resistance; performing the read-before-write (read-before-write (RBW), par. 37) operation on the selected memory cell according to the changed reference resistance; and writing the write data (step 610b, FIG. 6B) to the selected memory cell according to a result of the read-before-write operation (read-before-write (RBW), par. 37).
Regarding claim 16: Grobis discloses a resistive memory device (FIG. 1G), comprising: a cell array (memory arrays 174 and 176, FIG. 1G) comprising a plurality of magnetoresistive random-access memory (MRAM) cells; a row decoder (row decoder 162, FIG. 1E) configured to drive word lines (selects particular word lines, par. 43) of the plurality of MRAM cells in response to a row address (decodes row address and selects particular word lines, par. 43); a read/write circuit (read/write circuits 150, FIG. 1D) connected to bit lines (bit lines electrically coupled to read/write circuits 150, par. 43) or source lines of the cell array and configured to perform a read-before-write operation (read-before-write (RBW), par. 37) on a selected memory cell based on a reference resistance value of a reference resistance circuit during a selective write operation; and a control circuit (control circuits 108, FIG. 1B) configured to adjust the reference resistance value of the reference resistance circuit according to write data during the selective write operation.
Regarding claim 17: Grobis discloses a resistive memory device (FIG. 1G), wherein the read/write circuit (read/write circuits 150, FIG. 1D) comprises: a sense amplifier (read circuit 150, FIG. 1D; control circuits may include sense amplifier, par. 28) configured to detect existing data stored (read and determine state of memory cell, par. 37) in the selected memory cell by comparing the reference resistance value of the reference resistance circuit (step 610a, FIG. 6A) with a resistance value of the selected memory cell; and a write driver (write circuit 150, FIG. 1D) configured to program the write data into the selected memory cell (write process 600b, FIG. 6B) according to a result of the read-before-write operation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3, 9, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Grobis et al. (US 20210065791 A1) in view of Lee et al. (US 20240161824 A1).
Regarding claim 2: Grobis does not disclose a resistive memory device, wherein a first data corresponding to a first resistance value or a second data corresponding to a second resistance value greater than the first resistance value is stored in the at least one memory cell, and wherein the selective write controller configured to set the reference resistance circuit to a first changed reference resistance value subtracted by a specific margin from a default resistance value in response to a first request to write the first data.
Lee discloses a resistive memory device (resistive memory device, par. 3), wherein a first data (first value of data in memory cell 31, par. 81) corresponding to a first resistance value (an initial value e.g., first reference resistance value Rref1-, par. 72) or a second data corresponding to a second resistance value (e.g., third reference resistance value, Rref3, par. 86) greater than the first resistance value (third reference resistance value Rref3 greater than Rref1, par. 86) is stored in the at least one memory cell, and wherein the selective write controller configured to set the reference resistance circuit (reference resistance circuit 331, par. 86) to a first changed reference resistance value (e.g., first reference resistance value Rref1-, par. 72) subtracted by a specific margin (reference resistance value Rref1- may be controlled to a value e.g., second reference resistance value, Rref2 less than Rref1, par. 86, FIG. 9A) from a default resistance value in response to a first request to write (write command of operation, FIG. 10) the first data.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Grobis with the configuration of Lee to allow the device to adjust the memory cell resistance value by value of the reference resistance value.
Regarding claim 3: Grobis does not disclose a resistive memory device, wherein the selective write controller configured to set the reference resistance circuit to a second changed reference resistance value obtained by adding the specific margin to the default resistance value in response to a second request to write the second data.
Lee discloses a resistive memory device (resistive memory device, par. 3), wherein the selective write controller configured to set the reference resistance circuit (e.g., first reference resistance value Rref1-, par. 72; reference resistance circuit 331, par. 86) to a second changed reference resistance value obtained by adding the specific margin (reference resistance value Rref1- may be controlled to a value e.g., third reference resistance value, Rref3 greater than Rref1, par. 86, FIG. 9B) to the default resistance value in response to a second request to write (write command of operation, FIG. 10) the second data.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Grobis with the configuration of Lee to allow the device to adjust the memory cell resistance value by value of the reference resistance value.
Regarding claim 9: Grobis discloses a resistive memory device, wherein the at least one memory cell comprises a magnetic tunnel junction element (magnetic memory element Mx is a magnetic tunnel junction, par. 57, FIG. 2B).
Grobis does not disclose the memory cells comprising an access transistor.
Lee discloses a resistive memory device (resistive memory device, par. 3), wherein the at least one memory cell comprises an access transistor (MRAM cell may include a selection transistor alongside MTJ, par. 28, FIG. 2) alongside the MTJ.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the selector element Sx of Grobis with the selection transistor of Lee to allow the transistor of the memory cell to control access to the MTJ than the selector elements.
Regarding claim 11 and 18: Grobis does not disclose writing method of a resistive memory device, wherein the reference resistance is set to a default resistance value during a read operation and is set to either a first resistance value with a specific margin subtracted from the default resistance value or a second resistance value with the specific margin increased from the default resistance value during a selective writing operation.
Lee does disclose a writing method of a resistive memory device (resistive memory device, par. 3), wherein the reference resistance (reference resistance value of reference resistance circuit, par. 83) is set to a default resistance value (an initial value e.g., first reference resistance value Rref1-, par. 72) during a read operation (first reference resistance value set during a read operation, par. 72) and is set to either a first resistance value with a specific margin subtracted (reference resistance value Rref1- may be controlled to a value e.g., second reference resistance value, Rref2 less than Rref1, par. 86, FIG. 9A ) from the default resistance value or a second resistance value with the specific margin increased (reference resistance value Rref1- may be controlled to a value e.g., third reference resistance value, Rref3 greater than Rref1, par. 86, FIG. 9B) from the default resistance value during a selective writing operation (during write operation afterwards, par. 85).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Grobis with the configuration of Lee to allow the device to set the default resistance of the memory cell and adjust the memory cell resistance value by adding or subtracting a value of the reference resistance value.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2 A1) in view of Kim (US 20220084591 A1).
Regarding claim 8: Grobis does not disclose a resistive memory device, further comprising: a switch (control between write driver 240 and memory cell 252, FIG. 5) configured to connect the write driver (write driver 240, FIG. 5) to the at least one memory cell; and a comparator (comparator 251, FIG. 5) configured to compare the existing data (from VOUT, FIG. 5) with the write data (target data DIN, FIG. 5) to generate a switch control signal (VWRITE, FIG. 5) that connects or disconnects the write driver and the at least one memory cell (VWRITE controls the write driver, allowing the write driver modules to connect to target cells 231, par. 101-105), wherein the existing data is output from the sense amplifier (VOUT from amplifier 2511).
Kim does disclose a resistive memory device (200, FIG. 3), further comprising: a switch (control between write driver 240 and memory cell 252, FIG. 5) configured to connect the write driver (write driver 240, FIG. 5) to the at least one memory cell; and a comparator (comparator 251, FIG. 5) configured to compare the existing data (from VOUT, FIG. 5) with the write data (target data DIN, FIG. 5) to generate a switch control signal (VWRITE, FIG. 5) that connects or disconnects the write driver and the at least one memory cell (VWRITE controls the write driver, allowing the write driver modules to connect to target cells 231, par. 101-105), wherein the existing data is output from the sense amplifier (VOUT from amplifier 2511).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Grobis with the configuration of Kim to allow the connection between the memory cells and write drivers to be based on the current data and operation.
Allowable Subject Matter
Claims 4-7, 12-15, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject
matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having a multiplexer configured to select one of the specific margin and a zero margin according to an operation mode, and an adder/subtractor configured to set the reference resistance circuit by adding or subtracting an output of the multiplexer and the default resistance value according to the write data as in claim 4 and 19; a first multiplexer configured to select one of the specific margin and a zero margin according to an operation mode, an adder configured to add an output of the first multiplexer and the default resistance value, a subtractor configured to subtract the output of the first multiplexer from the default resistance value, and a second multiplexer configured to set the reference resistance circuit by selecting either an output of the adder or an output of the subtractor according to the write data as in claims 6 and 20; wherein if the write data is first data corresponding to a first resistance state lower than the default resistance value, the reference resistance is set to the first resistance value, and if the write data is second data corresponding to a second resistance state higher than or equal to the default resistance value, the reference resistance is set to the second resistance value as in claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/HOAI V HO/Primary Examiner, Art Unit 2827