DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the application filed August 14, 2024.
Thus, claims 1-20 are pending and are presenting for examination.
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1, 3-5, 9-12, and 16-20 are rejected under 35 U.S.C. 102(2) as being anticipated by Star et al. (US 20160232057 A1, hereinafter Star).
As per claims 1, 10, and 19, Star discloses a method for controlling a chip, comprising:
reading a first target code from a Read-Only Memory (ROM) of the chip -- (E.g., The host 302, controller 304 and the non-volatile memory (NVM) 312 are shown separately in FIG. 3, but in alternative embodiments they may be part of a single system (e.g. system on a chip SoC) …The ROM 306 may include firmware 308 that provides boot instructions” and “reading the original/regular boot loader” – see at least 0034, 0040, Fig. 3, Fig. 6, and associated text);
identifying whether the first target code is an exception code— (e.g., This self-detected malfunction can also cause the storage device to enter safe mode. The sensitive host data may include the original/regular boot loader or operating system files. The data corruption may include an identification of uncorrectable errors. In one example, the firmware may detect uncorrectable errors when reading the original/regular boot loader or other operating system logical sectors – see at least 0040, 402 of Fig. 4, and associated text) ;
not executing the first target code in response to the first target code being the exception code – (e.g., A malfunction may be detected in block 402. The malfunction may prevent the regular boot process -- see at least 0035, FIG. 4 and associated text); and
reading a second target code from a set storage space of the chip, and executing the second target code – (e.g., when safe mode is triggered, the host 302 accesses the firmware 308 in the ROM 306 which provides the location for the safe mode boot loader 316 on the NVM 312… The host utilizes the safe mode boot loader code to boot in safe mode – see at least 0034, 0036, Fig. 3, Fig. 4, and associated text).
Further regarding to claim 10, Star discloses a chip – (e.g., non-volatile memory system 100 -- see at least 0017, 0022, Fig. 1A and associated text) comprising: a central processing unit (CPU), a Read-Only Memory (ROM), and a set storage space; wherein the CPU is configured to implement method steps as of claim 1 above.
Further regarding to claim 19, Star discloses an electronic device (e.g., example of host systems such as PCs – see at least 0017), comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to implement method steps as of claim 1 above.
As per claims 3 and 16, Star discloses further comprising: obtaining a mapping relationship between identifiers of first candidate codes and identifiers of second candidate codes; obtaining an identifier of the first target code; and determining the second target code from a plurality of second candidate codes based on the identifier of the first target code and the mapping relationship – (e.g., the host performs a logical read of boot loader logical addresses (same addresses as regular boot-loader) to access the safe mode boot loader – see at least 0036).
As per claims 4 and 17, Star discloses wherein reading the second target code from the set storage space of the chip comprises: reading the second target code from a first storage space of the chip, wherein the first storage space is a storage space of non-executable codes; storing the read second target code in a second storage space of the chip, wherein the second storage space is a storage space of executable codes; and reading the second target code from the second storage space— (e.g. During safe mode, the safe mode boot loader 520 is loaded into the controller RAM 510 and is accessible to the host 502 for booting in safe mode -- see at least 0034, 0036, 0037 Figs. 3-5 and associated text).
As per claims 5 and 18, Star discloses further comprising: determining the second storage space based on the second target code -- (e.g. During safe mode, the safe mode boot loader 520 is loaded into the controller RAM 510 and is accessible to the host 502 for booting in safe mode -- see at least 0034, 0036, 0037 Figs. 3-5 and associated text).
As to claim 9, Star discloses further comprising: executing the first target code in response to the first target code being a non-exception code – (e.g., the host can access the regular boot loader and boot according to the regular (not safe mode) booting process in block 414. – see at least 0035-0035, Fig. 3, Fig. 4 and associated text).
As to claim 11, Star discloses wherein the set storage space comprises: a first storage space, wherein the first storage space is a storage space of non-executable codes; and a second storage space, wherein the second storage space is a storage space of executable codes-- (e.g. During safe mode, the safe mode boot loader 520 is loaded into the controller RAM 510 and is accessible to the host 502 for booting in safe mode -- see at least 0034, 0036, 0037 Figs. 3-5 and associated text).
As to claim 12, Star discloses wherein the first storage space comprises a one-time programmable memory – (e.g., A read only memory (ROM) 118 stores system boot code – see at least 0028).
As to claim 20, Star discloses a non-transitory computer-readable storage medium (e.g., Non-volatile storage medium – see at least 0020 and 0056), having computer program instructions stored thereon, wherein the program instructions, when executed by a processor, perform the method of claim 1.
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 2 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Star in view of WEN SUJIAN (WO 2019184159 A1, published on 2019-10-03, hereinafter Wen).
As per claims 2 and 15, it is to note that while Star discloses the safe mode is triggered when the original boot loader code is corrupted – see at least 0040 but does not explicitly disclose; however Wen, in analogous art, discloses wherein identifying whether the first target code is the exception code comprises: obtaining a code library, wherein each code in the code library is marked as the exception code; identifying whether the first target code exists in the code library; identifying that the first target code is the exception code in response to the first target code existing in the code library; and identifying that the first target code is a non-exception code in response to the first target code not existing in the code library –
(e.g., acquiring program code blocks generated by each user terminal, each program code block being corresponding to one user terminal identifier, and the different program code blocks sent by a same user terminal being corresponding to a same user terminal identifier; detecting, according to a historical abnormal code database, whether the program code blocks sent by the each user terminal contain an abnormal code which matches the historical abnormal
code of the historical abnormal code database; and when it is detected that a certain program code block contains an abnormal code corresponding to the historical abnormal
information in the historical abnormal code database, determining the user terminal identifier
corresponding to the program code block, and sending code abnormal warning information to the user terminal corresponding to the determined user terminal identifier. The method can prevent the problem that the program code return may occur after testing the environment on the program code block deployment) – see Wen, at least abstract.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated Wen’s teaching into Star’s teaching for further optimizing in identifying abnormal code; accordingly, promoting efficiencies in recognize corrupted code as seen in Wen (e.g., abstract).
9. Claims 6-8, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Star in view of Lam et al. (US 20160034397 A1, hereinafter Lam).
As to claim 6, it is to note that Star does not explicitly disclose, but Lam, in analogous art, discloses further comprising: determining that the second target code is a first type of code in response to a storage capacity occupied by the second target code being less than or equal to a set threshold; and determining that the second target code is a second type of code in response to the storage capacity occupied by the second target code being greater than the set threshold – (e.g., comparing storage spaces in size to a threshold in order to creating/ allocating storage spaces as such,
In a first possible implementation manner, each process of the application program has a separate on-chip storage scope in the on-chip memory; that is, an on-chip storage scope of a specific size in the on-chip memory of the computing node is allocated in advance to each process of the application program, where the size of the on-chip storage scope that is allocated in the on-chip memory to each process may be the same or may be different. In this case, the determining step in step S603 includes determining whether remaining space of an on-chip storage scope of the first process is less than a size of a backup page created in step S602 or is less than a second threshold. Correspondingly, if it is determined that the remaining space of the on-chip storage scope of the first process is less than the size of the backup page or is less than the second threshold, the first process is triggered to execute a comparison operation…stored the create …into the on-chip memory – See Lam, at least 0087-0089, 0090, Fig. 6, and associated text).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated Lam’s teaching into Star’s teaching for further optimizing and maintaining allocating space in boot loading execution process; accordingly, promoting efficiencies in execution and avoiding access latency as seen in Lam (e.g.,0010).
As to claim 7, modified Star with Lam discloses wherein determining the second storage space based on the second target code comprises: using a third storage space as the second storage space in response to the second target code being the first type of code; and using a fourth storage space as the second storage space in response to the second target code being the second type of code; wherein a storage capacity of the third storage space is less than a storage capacity of the fourth storage space – (e.g., incorporated Lam’s teaching of comparing storage spaces in size to a threshold in order to creating/ allocating storage spaces-- See Lam, at least 0087-0089, 0090, Fig. 6, and associated text, into Star’s teaching for further optimizing and maintaining allocating space in boot loading execution process; accordingly, promoting efficiencies in execution and avoiding access latency as seen in Lam (e.g.,0010)).
As to claim 8, modified Star with Lam discloses wherein in response to the second target code being the second type of code, before reading the second type of code from the fourth storage space, the method further comprises: reading a third target code from the first storage space, wherein the third target code is used for instructing to read the second type of code from the fourth storage space; storing the read third target code in the third storage space; and reading the third target code from the third storage space, and executing the third target code– (e.g., incorporated Lam’s teaching of comparing storage spaces in size to a threshold in order to creating/ allocating storage spaces-- See Lam, at least 0087-0089, 0090, Fig. 6, and associated text, into Star’s teaching for further optimizing and maintaining allocating space in boot loading execution process; accordingly, promoting efficiencies in execution and avoiding access latency as seen in Lam (e.g.,0010)).
As to claim 13, it is to note that Star does not explicitly disclose, but Lam, in analogous art, discloses wherein the second storage space comprises: a third storage space and a fourth storage space, wherein a storage capacity of the third storage space is less than a storage capacity of the fourth storage space– (e.g., comparing storage spaces in size to a threshold in order to creating/ allocating storage spaces as such,
In a first possible implementation manner, each process of the application program has a separate on-chip storage scope in the on-chip memory; that is, an on-chip storage scope of a specific size in the on-chip memory of the computing node is allocated in advance to each process of the application program, where the size of the on-chip storage scope that is allocated in the on-chip memory to each process may be the same or may be different. In this case, the determining step in step S603 includes determining whether remaining space of an on-chip storage scope of the first process is less than a size of a backup page created in step S602 or is less than a second threshold. Correspondingly, if it is determined that the remaining space of the on-chip storage scope of the first process is less than the size of the backup page or is less than the second threshold, the first process is triggered to execute
a comparison operation…stored the create …into the on-chip memory – See Lam, at least 0087-0089, 0090, Fig. 6, and associated text).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated Lam’s teaching into Star’s teaching for further optimizing and maintaining allocating space in boot loading execution process; accordingly, promoting efficiencies in execution and avoiding access latency as seen in Lam (e.g.,0010).
As to claim 14, modified Lam with Star discloses wherein the fourth storage space comprises a Random Access Memory (RAM) — (e.g., allocation space in RAM --see Lam, at least 0182-0183).
Conclusion
10. The prior art made of record and not relied upon (cited on 892 form) is considered pertinent to application disclosure.
Zhang (US-20230025728-A1) disclosed chip booting control method in order to ensure that the chip can function normally.
Hasbun (US-6205548-B1) disclosed updating a nonvolatile memory.
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARINA LEE whose telephone number is (571)270-1648. The examiner can normally be reached Monday to Friday (8 am to 4: 30 pm ET).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hyung S. Sough can be reached on (571)-272-6799. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MARINA LEE/Primary Examiner, Art Unit 2192
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