DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement filed 8/14/2024 has been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-12, and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koo (US 2014/0169096 A1).
Regarding claim 1, Koo discloses a memory device (figure 1, 100), comprising: a plurality of memory cells each connected to any one of a plurality of word lines, the any one of the plurality of word lines being a selected word line, and programmed to any one of a plurality of program states ([0007], a memory array including a plurality of memory cells; and a peripheral circuit configured to change a voltage level of a bit line connected to a program target cell according to a threshold voltage of the program target cell among the memory cells during a program operation); a row decoder (figure 1, 140) configured to apply a program voltage or a verify voltage to a selected word line from the plurality of word lines ([0041], row decoder may be configured to connect the global lines and the local lines DSL, WL0 to WLn, and SSL so that the operation voltages loaded at to the global lines may be transmitted to the local lines DSL, WL0 to WLn, and SSL of the memory block 110MB selected in the memory array in response to the row address signals RADD of the control circuit); and a plurality of page buffers (figure 1, 150) connected to the plurality of memory cells through a plurality of bit lines and configured to store precharge data used to determine a precharge voltage of a target bit line connected to a verify target memory cell among the plurality of bit lines while the program voltage is applied to the selected word line ([0042], each of the page buffer groups 150 may include a plurality of page buffers includes PB1 to PBk connected with the memory array 110 through the bit lines BLe1 to BLek, and BLo1 to Blok, and the page buffers PB1 to PBk of the page buffer group 150 may selectively precharge the bit lines BLe1 to BLek or BLo1 to Blok according to the data, which is input to be stored the data in the memory cells C0e1 to C0ek or C0o1 to C0ok, in response to the PB control signal PBCON of the control circuit 120).
Regarding claim 2, Koo discloses a sensing circuit configured to perform a check operation of determining pass or fail of a verify operation based on data sensed from the plurality of memory cells while the program voltage is applied to the selected word line ([0045], the ass/fail check circuit 180 may generate the pass/fail signal PFS in response to comparison result signals provided from the page buffers PB1 to PBk during the program verification operation performed after the program operation).
Regarding claim 3, Koo teaches that the plurality of page buffers store the precharge data after the check operation is completed ([0044], the page buffers PB1 to PBk may temporarily store the data in internal latch circuits included in the page buffers PB1 to PBk).
Regarding claim 4, Koo discloses where the row decoder is configured to, after applying the program voltage to the selected word line, perform an under drive operation of decreasing a voltage of the selected word line, and apply the verify voltage to the selected word line ([0041], row decoder may be configured to connect the global lines and the local lines DSL, and the program voltage Vpgm or the read voltage Vread may be applied to the local word line connected with the selected cell).
Regarding claim 5, Koo discloses that the plurality of page buffers precharge the target bit line based on the precharge data while the verify voltage is applied to the selected word line ([0042], page buffers PB1 to PBk of the page buffer group 150 may selectively precharge the bit lines BLe1 to BLek or BLo1 to Blok according to the data, which is input to be stored the data in the memory cells C0e1 to C0ek or C0o1 to C0ok, in response to the PB control signal PBCON of the control circuit).
Regarding claim 7, Koo discloses that each of the plurality of page buffers comprises a plurality of latches and stores the precharge data in any one of the plurality of latches ([0044], page buffers PB1 to PBk may temporarily store the data in internal latch circuits included in the page buffers PB1 to PBk).
Regarding claim 8, the limitations of the claim are rejected as the same reasons as set forth in claim 1.
Regarding claim 9, the limitations of the claim are rejected as the same reasons as set forth in claim 2.
Regarding claim 10, the limitations of the claim are rejected as the same reasons as set forth in claim 7.
Regarding claim 11, the limitations of the claim are rejected as the same reasons as set forth in claim 4.
Regarding claim 12, the limitations of the claim are rejected as the same reasons as set forth in claim 5.
Regarding claim 15, the limitations of the claim are rejected as the same reasons as set forth in claim 1.
Regarding claim 16, Koo teaches that the control logic is configured to precharge the first bit line based on the first precharge data through the first page buffer ([0052], a precharge circuit P1 may perform an operation of precharging the sensing node SO in response to a precharge signal PRECH_N) and to control the first page buffer to sense a current or voltage of the precharged first bit line while a verify voltage is applied to the selected word line ([0042], page buffers PB1 to PBk of the page buffer group 150 may selectively precharge the bit lines BLe1 to BLek or BLo1 to Blok according to the data, which is input to be stored the data in the memory cells C0e1 to C0ek or C0o1 to C0ok, in response to the PB control signal PBCON of the control circuit).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Koo (US 2014/0169096 A1) in view of Choi (US 2022/0270696A1).
Regarding claim 6, Koo differs from the claimed invention in not specifically teaching that the precharge data is used to precharge a bit line connected to a memory cell programmed to a program state to be verified first among the at least two program states when a verify operation for at least two of the plurality of program states is performed. However, Choi teaches control logic 130 may control the peripheral circuit 120 to perform a program verify operation on the plurality of memory cells for at least one program state among the plurality of program states so that the peripheral circuit 120 to perform a selected bit-line (Sel BL) scheme for precharging selected bit lines among the plurality of bit lines connected to the plurality of memory cells in the program verify operation for the target program state ([0073]-[0075]) in order to improve program operation performance. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Koo in having that the precharge data is used to precharge a bit line connected to a memory cell programmed to a program state to be verified first among the at least two program states when a verify operation for at least two of the plurality of program states is performed, as per teaching of Choi, in order to improve program operation performance.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Koo (US 2014/0169096 A1) in view of Lee (US 11,699,487 B2).
Regarding claim 13, Koo differs from the claimed invention in not specifically teaching the step of sensing a current or voltage of the first bit line after precharging the first bit line. However, Lee teaches the plurality of page buffers PB1 to PBm may sense a change of the amount of current that is flowing according to a program state of a corresponding memory cell through a sensing node while continuously supplying a sensing current to the bit lines that are connected to the memory cells (col. 4 lines 10-26) in order to prevent disturb. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Koo in having the step of sensing a current or voltage of the first bit line after precharging the first bit line, as per teaching of Lee, in order to prevent disturb.
Allowable Subject Matter
Claims 14 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach nor suggest “after sensing, setting precharge data for precharging a second bit line connected to a memory cell corresponding to a second program state among the plurality of bit lines in a second page buffer connected to the second bit line among the plurality of page buffers; applying a verify voltage for verifying the second program state to the selected word line; and precharging the second bit line based on the precharge data for precharging the second bit line through the second page buffer; and sensing a current or voltage of the second bit line” as recited in claim 14; and “wherein the control logic is configured to, after sensing the current or voltage of the precharged first bit line, control a second page buffer connected to a second bit line among the plurality of bit lines, among the plurality of page buffers, to set second precharge data used to determine a precharge voltage of the second bit line” as recited in claim 17.
Claim 18 is object because of depending to claim 17, containing the same allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mun et al. (US 2023/0062706 A1) discloses a memory device and method of operation includes memory cells and a program operation performer configured to perform a verify operation and a program voltage apply operation (abstract and figure 2).
Kim et al. (US 2022/0189557 A1) discloses a memory device including: a plurality of memory cells each having a threshold voltage corresponding to any one of a plurality of program states according to target data to be stored by performing a program operation, page buffers configured to temporarily store data provided from a memory controller, a data conversion controller configured to control the page buffers to convert the data into the target data including a plurality of logical page bits and a program operation controller configured to perform the program operation to store the target data in the plurality of memory cells (abstract and figure 2).
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/ZHUO H LI/ Primary Examiner, Art Unit 2133