Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
DETAILED ACTION
2. This is the initial Office Action based on the application filed onAugust14, 2024. The current application is a continuation of application 18/342504, now patent US 12,137,294 B2 (issued on 11/05/2024), which is a continuation of application 17/735246, now patent US 11,729,530 B2 (issued on 08/15/2023), which is a continuation of application 17/315014, now patent US 11,343,455 B2 (issued on 05/24/2022), which is a continuation of application 16/844670, now patent US 11,032,504 B2 (issued on 06/08/2021), which is a continuation of application 16/055377, now patent US 10,645,321 B2 (issued on 05/05/2020), which is a continuation of application 15/671227, now patent US 10,044,962 B2 (allowed on 08/07/2018), which is a continuation of application 15/146099, now patent US 9,762,832 B2 (allowed on 09/12/2017), which is a continuation of application 14/363971, now patent US 9,363,451 B2 (allowed on 06/07/2016). The Examiner acknowledges the following:
3. Claims 1 – 8 were filed.
4. The amended drawings filed on 08/14/2024 are accepted by the Examiner.
5. Current claims 1 – 8 are pending and they are being considered for examination.
Information Disclosure Statement
6. The IDS documents filed on 09/11/2024 and 09/25/2024 are acknowledged by the Examiner.
Priority
7. Priority documents referring to a PCT application document PCT/JP2012/081755 with filing date 12/07/2012 and a Japanese application JP-2011-277076 with foreign priority date of December 19, 2011. Certified copies were filed to the office with application 14/363971, on 06/09/2014.
Claim Rejection under 35 U.S.C. 112(b)
8. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Regarding Claims 4 – 5:
Claim 4 recites ”The light detecting device according to claim 1, wherein the photoelectric conversion unit is located in the semiconductor layer, the transfer gate is located on a sidewall of a concave portion, formed by processing the surface layer of the semiconductor layer along …”.
There is no semiconductor layer in claim 1. It is unclear what does Applicant mean for it or what he/she is trying to get as a result of his/her invention. Claim 4 is rejected under U.S.C. 112(b) for lack of antecedent basis for it.
Claim 5 depends on claim 4 and it includes the same “the semiconductor Layer” and it is rejected under the same rationale as discussed above for claim 4.
Double Patenting
9. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Omum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321 (c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
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5. Instant Application great-great-great-great-great-great-great-parent application 14/363971 (US 9,363,451 B2) allowed on June 07, 2016 have a Double Patent issue.
Regarding Claims 1 – 8:
Claims 1 – 8 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1 – 8 of parent application 14/363971 (US 9,363,451 B2), allowed on June 07, 2016 in view of Chau (US 2004/0036226 A1) and Itonaga (US 2006/0275990 A1).
As indicated in Table 1 below as for the underlined portion/limitations of claims 1 – 8 of great-great-great-great-great-great-great-parent are very similar to present claims 1 – 8 combined and they were already claimed in the great-great-great-great-great-great-great -parent patent 9,363,451 B2. Just because Applicant changed the “imaging device” of parent claim 1 by “light detecting device” in the great-great-great-great-great-great-great-child application, it does not make the child application patentably distinct from each other, since according to the invention being disclosed and as indicated in Fig 1, which shows
the light detecting device corresponds to an imaging device with pixel area 4 including pixels 3 that detect the incident light (See Fig 1) and the photodiode PD, floating diffusion region FD or first semiconductor region as part of the store region 35, transfer gate TRG (See Fig 1). TG designed to extend along the sidewall of the concave region 31. As for clarity these limitations are set in bolded and underlined on Table I: 1. Transfer charge from PD to the floating diffusion this is what transfer gates do; 2. Insulating film: this is common procedure to do when dealing with electric connections and circuits; to insulate the electric contacts to prevent leakage or damage to the connections. These limitations do not add any patentable limitations to the claim disclosure. See Table I for clarity, wherein the aforementioned terms are identified in bolded and underlined.
Therefore, claims 1 – 8 are rejected under nonstatutory obviousness-type double patenting in view of the references cited, and it is anticipated and fully encompassed by claims 1 – 8 of the great- great-great-great-great-great-great-parent issued patent 9,363,451 B2.
Note: Please, see Table I for the comparison between the claims of the great-great-great-great-great-great-great-parent patent US 9,363,451 B2 (1st column) and the present application as the apparatus claims (2nd column). The underlined portions in both columns indicate what is equivalent in the parent and in the current application.
Table I: Comparison between the parent application 14/363971 (US 9,363,451 B2) and child application 18/804704
Great-great-great-great parent 14/363971- now US 9,363,451 B2
child 18/804704
1. A solid-state imaging device comprising: a photoelectric conversion device;
a transfer gate configured to read out charges from the photoelectric conversion device;
a floating diffusion from which the charges of the photoelectric conversion device are read by an operation of the transfer gate; and
an amplifying transistor of a fully-depleted type connected to the floating diffusion, wherein the amplifying transistor includes:
2. The solid-state imaging device according to claim 1, wherein a channel portion of the amplifying transistor is formed with an intrinsic semiconductor.
a convex strip formed by processing a surface layer of a semiconductor layer; and a gate electrode on the semiconductor layer, the gate electrode extending in a direction perpendicular to the convex strip.
A light detecting device comprising: a photoelectric conversion unit;
a transfer gate configured to read out charges from the photoelectric conversion unit;
a floating diffusion from which the charges of the photoelectric conversion unit are read by an operation of the transfer gate; and
an amplifying transistor connected to the floating diffusion,
wherein a channel portion of the amplifying transistor comprises an intrinsic semiconductor.
2. The light detecting device according to claim 1, wherein the amplifying transistor includes: a convex strip formed by processing a surface layer of a semiconductor layer; and a gate electrode on the semiconductor layer, the gate electrode extending in a direction perpendicular to the convex strip.
3. The solid-state imaging device according to claim 1, wherein a plurality of convex strips are arranged in parallel, each of the convex strips being the same as the convex strip, and the gate electrode extends in a direction perpendicular to the convex strips.
3. The light detecting device according to claim 2, wherein a plurality of convex strips are arranged in parallel, each of the convex strips being the same as the convex strip, and the gate electrode extends in a direction perpendicular to the convex strips.
4. The solid-state imaging device according to claim 1, wherein the photoelectric conversion device is located in the semiconductor layer, the transfer gate is located on a sidewall of a concave portion formed by processing the surface layer of the semiconductor layer along the photoelectric conversion device, and the floating diffusion is located at a bottom portion of the concave portion.
4. The light detecting device according to claim 1, wherein the photoelectric conversion unit is located in the semiconductor layer, the transfer gate is located on a sidewall of a concave portion formed by processing the surface layer of the semiconductor layer along the photoelectric conversion unit, and the floating diffusion is located at a bottom portion of the concave portion.
Claim 1:
a convex strip formed by processing a surface layer of a semiconductor layer; and a gate electrode on the semiconductor layer, the gate electrode extending in a direction perpendicular to the convex strip.
5. The solid-state imaging device according to claim 4, wherein the amplifying transistor includes: a step formed by the concave portion is equal in height to a step formed by the convex strip.
5. The light detecting device according to claim 4, wherein the amplifying transistor includes: a convex strip formed by processing a surface layer of the semiconductor layer; and a gate electrode on the semiconductor layer, the gate electrode extending in a direction perpendicular to the convex strip, and
a step formed by the concave portion is equal in height to a step formed by the convex strip.
6. The solid-state imaging device according to claim 1, wherein the photoelectric conversion device includes:
an exposed-type photoelectric conversion device formed in a surface layer of the semiconductor layer; and
an embedded-type photoelectric conversion device buried in the semiconductor layer in such a manner as to be stacked on the exposed-type photoelectric conversion device, the embedded-type photoelectric conversion device facing a bottom face of a concave portion formed in the semiconductor layer, and
the floating diffusion includes:
a floating diffusion formed in a surface layer of the semiconductor layer, the floating diffusion being located close to the exposed-type photoelectric conversion device, and a floating diffusion formed in a bottom face layer of the concave portion,
the floating diffusion being located close to the embedded-type photoelectric conversion device.
6. The light detecting device according to claim 1, wherein the photoelectric conversion unit includes:
an exposed-type photoelectric conversion unit formed in a surface layer of the semiconductor layer; and
an embedded-type photoelectric conversion unit buried in the semiconductor layer in such a manner as to be stacked on the exposed-type photoelectric conversion unit, the embedded-type photoelectric conversion unit facing a bottom face of a concave portion formed in the semiconductor layer, and
the floating diffusion includes:
a floating diffusion formed in a surface layer of the semiconductor layer, the floating diffusion being located close to the exposed-type photoelectric conversion unit, and a floating diffusion formed in a bottom face layer of the concave portion,
the floating diffusion being located close to the embedded-type photoelectric conversion unit.
Claim 1:
a convex strip formed by processing a surface layer of a semiconductor layer; and a gate electrode on the semiconductor layer, the gate electrode extending in a direction perpendicular to the convex strip.
5. The solid-state imaging device according to claim 4, wherein the amplifying transistor includes: a step formed by the concave portion is equal in height to a step formed by the convex strip.
7. The light detecting device according to claim 6, wherein the amplifying transistor includes: a convex strip formed by processing a surface layer of the semiconductor layer; and a gate electrode on the semiconductor layer, the gate electrode extending in a direction perpendicular to the convex strip, and
a step formed by the concave portion is equal in height to a step formed by the convex strip.
8. The solid-state imaging device according to claim 6, wherein a photoelectric conversion device formed with a photoelectric conversion film is placed on a reverse face of the semiconductor layer while being stacked on the photoelectric conversion device.
8. The light detecting device according to claim 6, wherein a photoelectric conversion unit formed with a photoelectric conversion film is placed on a reverse face of the semiconductor layer while being stacked on the photoelectric conversion unit.
In conclusion, instant application claims 1 – 8 are rejected under nonstatutory obviousness-type double patenting in view of the references cited, and they are anticipated and fully encompassed by claims 1 – 8 of the great-great-great-great-great-great-great-parent issued patent 9,363,451 B2.
Conclusion
10. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
1. Y. Kawahara et al., US 2025/0169211 A1 – it includes the same assignee and different inventor(s). It teaches a semiconductor device, comprising: a semiconductor substrate; and a field-effect transistor provided on the semiconductor substrate, wherein: the field-effect transistor includes a diffusion layer region in which a channel is formed, a gate electrode portion covering at least a part of the diffusion layer region and having a side wall portion facing a side surface of the diffusion layer region and a top plate portion facing an upper surface of the diffusion layer region, a source region provided in the diffusion layer region and connected to one side of the gate electrode portion in a gate length direction of the gate electrode portion, and a drain region provided in the diffusion layer region and connected to the other side of the gate electrode portion in the gate length direction of the gate electrode portion; the side wall portion and the top plate portion of the gate electrode portion have a self-aligned structure; and the source region and the drain region are formed to be self-aligned by implanting impurities obliquely into the side wall portion of the gate electrode portion.
Contact
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARLY S.B. CAMARGO whose telephone number is (571)270-3729. The examiner can normally be reached on M-F 8:00-5:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached on 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MARLY S CAMARGO/Primary Examiner, Art Unit 2638