DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito et al. (US Publication 2017/0301474) in view of Hattori et al. (WO2016035590A1).
In re claim 1, Saito discloses an electronic component comprising:
a substrate (200 – Figure 3, ¶25);
a plurality of multilayer capacitors (311, 312 – Figure 3, ¶25) mounted on a mounting surface of the substrate (Figure 3); and
wherein each of the plurality of multilayer capacitors includes:
an element body (¶26) having formed a plurality of dielectric layers (space between 211c, 212c - - Figure 3, ¶24) stacked and having a pair of end surfaces and four side surfaces coupling the pair of end surfaces (Figure 3);
an external electrode (211a, 211b, 212a, 212b – Figure 3, ¶24) arranged on the element body (Figure 3); and
a plurality of internal electrodes (211c, 212c – Figure 3) arranged in the element body and arranged to be opposed to each other in a stacking direction of the plurality of dielectric layers (Figure 3), the external electrode (211a, 211b, 212a, 212b – Figure 3) of the multilayer capacitor being mounted on the substrate by solder (¶27), and wherein at least a part of adjacent multilayer capacitors overlaps each other when viewed from a direction in which the pair of side surfaces of the element body are opposed to each other (See Figure 3),
the direction being along the mounting surface of the substrate, in the adjacent multilayer capacitors, stacking directions of the plurality of internal electrodes are the same (Figure 3), and a distance between the adjacent multilayer capacitors is 1/2 or less of a height of the multilayer capacitor mounted on the substrate (See Figure 4: Sample IN200 having a value of 0.1 mm with a component size of 0603 or 1005).
Saito does not disclose a sealing part formed of a resin and sealing the plurality of multilayer capacitors.
Hattori discloses a sealing part (R – Figure 5, Figure 13, Figure 14, ¶298) formed of a resin (¶289) and sealing the plurality of multilayer capacitors (10 – Figure 5, Figure 13, Figure 14, ¶73).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the sealing resin of Hattori to protect the electronic component from external environmental factors and to decrease the vibration of the electronic component.
In re claim 2, Saito in view of Hattori discloses the electronic component according to claim 1, as explained above. Saito further discloses wherein each of the plurality of multilayer capacitors (211, 212 – Figure 3) has the same configuration, shape, and dimension, and the plurality of multilayer capacitors are arranged so as to overlap each other when viewed from the direction in which the pair of side surfaces of the element body are opposed to each other (Figure 3), the direction being along the mounting surface of the substrate (Figure 3) (See Figure 4: Sample IN200 having a value of 0.1 mm with a component size of 0603 or 1005).
In re claim 3, Saito in view of Hattori discloses the electronic component according to claim 1, as explained above. Saito further discloses wherein the multilayer capacitor (211, 212 – Figure 3) is arranged so as to have the stacking direction of the plurality of internal electrodes (211c, 212c – Figure 3) orthogonal to the mounting surface (Figure 3).
In re claim 4, Saito in view of Hattori discloses the electronic component according to claim 1, as explained above. Saito further discloses wherein and the element body has a length in the stacking direction of 1.0 mm or more (See Figure 4: Sample IN200 having a value of 0.1 mm with a component size of 2012.).
Saito does not disclose the number of the dielectric layers stacked of the multilayer capacitor is 100 or more. However it is well-known in the art that adjusting the number of dielectric layers is directly correlated with the capacitance of the device. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the number of dielectric layers to achieve a device having desired capacitance, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
In re claim 5, Saito in view of Hattori discloses the electronic component according to claim 1, as explained above. Saito does not disclose wherein a distance between the mounting surface of the substrate and the element body of the multilayer capacitor opposed to the mounting surface is 0.2 mm or less, and the sealing part is arranged between the mounting surface and the element body.
Hattori discloses wherein a distance between the mounting surface of the substrate (upper surface of B – Figure 2, Figure 13, ¶71) and the element body (CP1l – Figure 2, Figure 13, ¶74) of the multilayer capacitor opposed to the mounting surface is 0.2 mm or less (¶101), and the sealing part (R – Figure 2, Figure 13) is arranged between the mounting surface and the element body (Figure 2, Figure 13).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the height of the sealing body and multilayer capacitor, and thus, distance between the mounting surface and the element body, to reduce the vibration of the substrate (¶23, ¶97-101).
In re claim 6, Saito in view of Hattori discloses the electronic component according to claim 1, as explained above. Saito does not disclose wherein the resin is a silicone resin or an epoxy resin.
Hattori discloses wherein the resin is a silicone resin or an epoxy resin (¶153).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the sealing resin of Hattori to protect the electronic component from external environmental factors and to decrease the vibration of the electronic component.
In re claim 7, Saito in view of Hattori discloses the electronic component according to claim 1, as explained above. Saito does not disclose wherein a height of the sealing part from the mounting surface is twice or more a height of the multilayer capacitor mounted on the mounting surface.
Hattori discloses a height of the sealing part from the mounting surface is twice or more a height of the multilayer capacitor mounted on the mounting surface (¶97, ¶101).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the sealing resin of Hattori to protect the electronic component from external environmental factors and to decrease the vibration of the electronic component.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bultitude (US Patent 8,028,397) Figure 1, Figure 3
Hattori et al. (US Publication 2014/0043723) Figure 1B
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARUN RAMASWAMY whose telephone number is (571)270-1962. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
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/ARUN RAMASWAMY/Primary Examiner, Art Unit 2848
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