DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 requires a first control signal and a second control signal. Claim 10, which depends from claim 8, also cites “a first control signal” and “a second control signal.” Hence, it is unclear whether the control signals of claim 10 are intended to correspond to the control signals of claim 8 or whether they are distinct.
For the purposes of examination, examiner will interpret all instances of “a first control signal” and “a second control signal” in claim 10 as “the first control signal” and “the second control signal”, respectively.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 8-9 and 15-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh (US 2007/0285132).
For claim 1, Oh teaches a phase locked loop circuit (Figure 8) comprising:
a phase-frequency detection circuit (810, 820, 840, 861, 863, 864) configured to:
receive a reference clock signal (CKin) and a feedback clock signal (CKout),
adjust a phase gain (via 810, 820, 840) based on a first phase difference between the reference clock signal and the feedback clock signal being less than a reference value (value to enter a locked state, as explained below) and
generate a first control signal (XUP, UP) and a second control signal (XDN, DN) based on the phase gain (as understood by examination of Figure 8);
a lock detection circuit (830) configured to generate a lock detection signal (output of 830) that is activated based on the first phase difference being less than the reference value (as understood by examination of Figure 8 and as further explained below);
a charge pump circuit (760) configured to generate a loop filter input signal (signal at top terminal of 871) by precharging an output node (output node of 760) based on the first control signal and discharging the output node based on the second control signal (as understood by examination of Figure 8);
a loop filter (870) comprising at least one resistor (R1, R2) and at least one capacitor (C1, C2), the loop filter configured to:
adjust impedance (enable/disable switch within 870) based on the activated lock detection signal (875 controls switchable resistor R2, operation of 875 is based on XUP and XDN which are based on the lock detection signal, as understood by examination of Figure 8 and as further explained below), and
generate a loop filter output signal (input to 880) by filtering the loop filter input signal based on the adjusted impedance (as understood by examination of Figure 8);
an oscillator (880) configured to generate a clock signal based on the loop filter output signal (CKvco); and
a divider (890) configured to generate the feedback clock signal by dividing the clock signal (as understood by examination of Figure 8).
Applicant’s Specification defines phase gain as “the ratio of the input phase difference and the output phase difference” ([0030]).
Oh teaches that “the lock detector 830 receives the first up-signal UP and the first down-signal DN and outputs an inverted lock signal LOCKb that is deactivated when the first up-signal UP and the first down-signal DN are simultaneously logic `low.’ The up-signal output unit 840 outputs an up-signal XUP that is deactivated when the first up-signal UP, the second up-signal [NUP] and the inverted lock signal LOCKb are simultaneously logic `low.` ([0072]-[0073]).
Hence, only one pair of phase detector output signals (XUP and XDN or UP and DN) are used to control charge pump 760 at a time such that either the left branch of 760 (both instances of 861, 863, 864) or the right branch of 760 (both instances of 862, 865, 866) is alternatively selected to generate Vctl based on the lock detection state.
Oh further teaches that “the lock detector, according to an example embodiment of the present invention, outputs the lock signal in accordance with the reduced phase difference when the up-signal UP and the down-signal DN become locked.” ([0081]).
Although the claimed reference value is not explicitly stated in Oh, a phase difference threshold is inherently required to detect a locked state.
For claim 2, Oh further teaches:
based on the lock detection signal being in an inactive state, a resistance value of the at least one resistor having a first resistance value (when R2 is not in parallel with R1 by disabling the switch within 870),
wherein based on the lock detection signal being in an activated state, a resistance value of the at least one resistor having a second resistance value (based on R1 and R2 in parallel), and
wherein the first resistance value is greater than the second resistance value ([0076]).
For claim 8, Oh teaches a method of operating a phase-locked loop circuit (Figure 8), the method comprising:
adjusting a phase gain (via 810, 820, 840) based on a first phase difference between a reference clock signal (CKin) and a feedback clock signal (CKout),
generating a first control signal (XUP, UP) and a second control signal (XDN, DN) based on the adjusted phase gain (as understood by examination of Figure 8);
generating a lock detection signal (output of 830) based on the first phase difference (as understood by examination of Figure 8), the lock detection signal being activated based on the first phase difference being less than or equal to a reference value and the lock detection signal being deactivated based on the first phase difference exceeding the reference value (as further explained below);
generating (via 760) a loop filter input signal (signal at top terminal of 871) by precharging an output node (output node of 760) based on the first control signal and discharging the output node based on the second control signal (as understood by examination of Figure 8);
adjusting (enable/disable switch within 870) an impedance of a loop filter (870) based on the lock detection signal (875 controls switchable resistor R2, operation of 875 is based on XUP and XDN which are based on the lock detection signal, as understood by examination of Figure 8 and as further explained below);
generating a loop filter output signal (input to 880) by filtering the loop filter input signal based on the adjusted impedance (as understood by examination of Figure 8); and
generating (via 880) a clock signal (CKvco) based on the loop filter output signal.
Applicant’s Specification defines phase gain as “the ratio of the input phase difference and the output phase difference” ([0030]).
Oh teaches that “the lock detector 830 receives the first up-signal UP and the first down-signal DN and outputs an inverted lock signal LOCKb that is deactivated when the first up-signal UP and the first down-signal DN are simultaneously logic `low.’ The up-signal output unit 840 outputs an up-signal XUP that is deactivated when the first up-signal UP, the second up-signal [NUP] and the inverted lock signal LOCKb are simultaneously logic `low.` ([0072]-[0073]).
Hence, only one pair of phase detector output signals (XUP and XDN or UP and DN) are used to control charge pump 760 at a time such that either the left branch of 760 (both instances of 861, 863, 864) or the right branch of 760 (both instances of 862, 865, 866) is alternatively selected to generate Vctl based on the lock detection state.
Oh further teaches that “the lock detector, according to an example embodiment of the present invention, outputs the lock signal in accordance with the reduced phase difference when the up-signal UP and the down-signal DN become locked.” ([0081]).
Although the claimed reference value is not explicitly stated in Oh, a phase difference threshold is inherently required to detect a locked state.
For claim 9, Oh further teaches:
the adjusting of the impedance of the loop filter comprises reducing a resistance value included in the loop filter based on the activated lock detection signal (as understood by examination of Figure 8 and [0076]).
For claim 15, Oh teaches a phase locked loop circuit (Figure 8) comprising:
a phase-frequency detection circuit (810, 820, 840, 861, 863, 864) configured to:
receive a reference clock signal (CKin) and a feedback clock signal (CKout),
adjust a phase gain (via 810, 820, 840) based on a first phase difference between the reference clock signal and the feedback clock signal being less than a reference value (value to enter a locked state, as explained below) and
generate a first control signal (XUP, UP) and a second control signal (XDN, DN) based on the phase gain (as understood by examination of Figure 8);
a lock detection circuit (830) configured to generate a lock detection signal (output of 830) that is activated based on the first phase difference being less than the reference value (as understood by examination of Figure 8 and as further explained below);
a charge pump circuit (760) configured to generate a loop filter input signal (signal at top terminal of 871) by precharging an output node (output node of 760) based on the first control signal and discharging the output node based on the second control signal (as understood by examination of Figure 8);
a loop filter (870) comprising at least one resistor (R1, R2) and at least one capacitor (C1, C2), the loop filter configured to:
adjust a resistance value of the at lease one resistor or a capacitance value of the at least one capacitor (adjust resistance via switch within 870) based on the activated lock detection signal (875 controls switchable resistor R2, operation of 875 is based on XUP and XDN which are based on the lock detection signal, as understood by examination of Figure 8 and as further explained below), and
generate a loop filter output signal (input to 880) by filtering the loop filter input signal based on the adjusted resistance value (as understood by examination of Figure 8); and
an oscillator (880) configured to generate a clock signal based on the loop filter output signal (CKvco).
Applicant’s Specification defines phase gain as “the ratio of the input phase difference and the output phase difference” ([0030]).
Oh teaches that “the lock detector 830 receives the first up-signal UP and the first down-signal DN and outputs an inverted lock signal LOCKb that is deactivated when the first up-signal UP and the first down-signal DN are simultaneously logic `low.’ The up-signal output unit 840 outputs an up-signal XUP that is deactivated when the first up-signal UP, the second up-signal [NUP] and the inverted lock signal LOCKb are simultaneously logic `low.` ([0072]-[0073]).
Hence, only one pair of phase detector output signals (XUP and XDN or UP and DN) are used to control charge pump 760 at a time such that either the left branch of 760 (both instances of 861, 863, 864) or the right branch of 760 (both instances of 862, 865, 866) is alternatively selected to generate Vctl based on the lock detection state.
Oh further teaches that “the lock detector, according to an example embodiment of the present invention, outputs the lock signal in accordance with the reduced phase difference when the up-signal UP and the down-signal DN become locked.” ([0081]).
Although the claimed reference value is not explicitly stated in Oh, a phase difference threshold is inherently required to detect a locked state.
For claim 16, Oh further teaches:
based on the lock detection signal being in an inactive state, a resistance value of the at least one resistor having a first resistance value (when R2 is not in parallel with R1 by disabling the switch within 870),
wherein based on the lock detection signal being in an activated state, a resistance value of the at least one resistor having a second resistance value (based on R1 and R2 in parallel), and
wherein the first resistance value is greater than the second resistance value ([0076]).
Allowable Subject Matter
Claims 3-7, 11-14 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CALRISSIAN PUENTES whose telephone number is (571)270-5070. The examiner can normally be reached M-F 9-6:30 (flex).
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/DANIEL C PUENTES/Primary Examiner, Art Unit 2849