DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 13 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (United States Patent Application Publication No. US 2023/0005884 A1, hereinafter “Park”).
In reference to claim 13, Park discloses a device which meets the claim. Fig. 22A and 22B of Park disclose a semiconductor package which comprises a package substrate (100). A first buffer chip (200a) is on the package substrate (100). An upper surface of the first buffer chip (200a) has a rectangular shape. There is a second buffer chip (200b) to the right and adjacent to the first buffer chip (200a) in a first direction (D2). There is a first chip stack structure (CS1, CS2) in which a first plurality of memory chips (110, 120) are stacked (p. 2, paragraphs 41-42). The first chip stack structure (CS1, CS2) is to the left and adjacent to the first buffer chip (200a) in the first direction (D2) on the package substrate (100). There is a second chip stack structure (CS3, CS4) in which a second plurality of chips (130, 140) are stacked. The second plurality of chips (130, 140) are memory chips (p. 2, paragraphs 41-42). The second chip stack structure (CS3, CS4) is to the right and adjacent to the second buffer chip (200b) in the first direction (D2) on the package substrate (100).
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Annotated fig. 22A shows that the first buffer chip (200a) comprises a left first chip pad extending in a second direction (D1) perpendicular to the first direction (D2) along a left edge of an upper surface of the first buffer chip (200a) in the first direction (D2) and a right first chip pad extending along a right edge of the upper surface of the first buffer chip (200a) in the first direction (D2). The second buffer chip (200b) comprises a left second chip pad extending in the second direction (D1) along a left edge of an upper surface of the second buffer chip (200b) in the first direction (D2) and a right second chip pad extending in the second direction (D1) along a right edge of the upper surface of the second buffer chip (200b) in the first direction (D2). The right first chip pad is symmetrical to the left second chip pad.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Disney et al. (United States Patent Application Publication No. US 2009/0102493 A1, hereinafter “Disney”).
In reference to claim 1, Park discloses a similar device. Fig. 22A and 22B of Park disclose a semiconductor package which comprises a package substrate (100). There is a chip unit comprising a first semiconductor chip (200a) on a left portion of the package substrate (100 in a first direction (D2) and a second semiconductor chip (200b) on a right portion of the package substrate (100 in the first direction. There is a first chip stack structure (CS1, CS2) in which a first plurality of memory chips (110, 120) are stacked (p. 2, paragraphs 41-42). The first chip stack structure (CS1, CS2) is leftward and adjacent to the first semiconductor chip (200a) in the first direction (D2) on the package substrate (100). There is a second chip stack structure (CS3, CS4) in which a second plurality of chips (130, 140) are stacked. The second plurality of chips (130, 140) are memory chips (p. 2, paragraphs 41-42). The second chip stack structure (CS3, CS4) is rightward and adjacent to the second semiconductor chip (200b) in the first direction (D2) on the package substrate (100). In annotated fig. 22A below, the first semiconductor chip (200a) comprises a first chip body (200a), a left first chip pad extending in a second direction (D1) perpendicular to the first direction (D2) along a left edge of an upper surface of the first chip body (200a) in the first direction (D2) and a right first chip pad extending along a right edge of the upper surface of the first chip body (200a) in the first direction (D2). The second semiconductor chip (200b) comprises a second chip body (200b), a left second chip pad extending in the second direction (D1) along a left edge of an upper surface of the second chip body (200b) in the first direction (D2) and a right second chip pad extending in the second direction (D1) along a right edge of the upper surface of the second chip body (200b) in the first direction (D2). The left first chip pad is connected to the first chip stack structure (CS1, CS2) and the right first chip pad is connected to a substrate pad (note ovular pad to the right) included in the package substrate (100). The left second chip pad is connected to the substrate pad, and the right second chip pad is connected to the second chip stack structure, wherein the right first chip pad is symmetrical to the left second chip pad.
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Park does not disclose that the right first chip pad and the left second chip pad are connected to the substrate pad using a single-point type connection. However Park discloses that the left second chip pad and the right first chip pad are power/ground pads for the chips (p. 2, paragraph 38). Thus the substrate pad in the above annotated fig. 22A is a power/ground pad for the device. Disney discloses using a commonly connected or a single-point type connection pad instead of separate pads for a common signal in order to save package area and cost (p. 2, paragraph 19). In view of Disney, it would therefore be obvious for the first semiconductor chip (200a) and the second semiconductor chip (200b) to be commonly connected or use a single-point type connection to the same substrate pad which itself is connected to power/ground in order to save package area and cost. Thus claim 1 is not patentable over Park and Disney.
With regard to claim 2, fig. 22A of Park shows that the right first chip pad is point symmetrical to the left second chip pad thus the right first chip pad and the left second chip pad each comprises a mirror pad.
In reference to claim 12, in fig. 22A of Park, the first semiconductor chip (200a) and the second semiconductor chip (200b) are buffer chips (p. 4, paragraphs 83-84). Each memory chip of the first plurality of memory chips (110, 120) and the second plurality of memory chips (130, 140) is a flash memory chip (p. 2, paragraph 42).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Disney as applied to claim 1 above and further in view of Beauchamp et al. (United States Patent Application Publication No. US 2004/0021192 A1, hereinafter “Beauchamp”).
In reference to claim 5, in the device of Park constructed in view of Disney, the left first chip pad is connected to the first chip stack structure by a first wire, wherein the right second chip pad is connected to the second chip stack structure by a second wire as seen below in annotated fig. 22A of Park.
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In the device of Park constructed in view of Disney, the right first chip pad and the left second chip pad are connected to the substrate pad. None of the above references discloses that a single third wire connects the right first chip pad and the left second chip pad to the substrate pad. However fig. 4 of Beauchamp discloses using a single bonding wire (410b) to connect three conductive structures (104b, 104c, 106c) to each other. Beauchamp discloses that this uses only one common interconnection (p. 1, paragraph 8). Beauchamp further discloses that limiting the amount of connections in the package is desirable in order to stay within size and cost constraints (p. 1, paragraph 4). Thus in view of Beauchamp, it would therefore be obvious to use a single third wire to commonly connect the right first chip pad and the left second chip pad to the substrate pad.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Disney and further in view of Beauchamp as applied to claim 5 above and further in view of Min et al. (United States Patent Application Publication No. US 2022/0322527 A1, hereinafter “Min”).
With regard to claim 6, fig. 22A of Park shows that the substrate pad is on an upper surface of the package substrate (100) between the first semiconductor chip (200a) and the second semiconductor chip (200b). Park does not disclose that the substrate pad is shaped such that it extends in the second direction (D1). Although Park does not teach the exact shape of the substrate pad as that claimed by the applicant:
The shape, size, dimension differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious. Note In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Therefore this limitation is not patentable over the above cited references. Fig. 22B of Park discloses a lower substrate pad (note unlabeled pads in direct contact with upper surface of 105) on a lower surface of the package substrate (100). Park does not disclose that the lower substrate pad (note unlabeled pads in direct contact with upper surface of 105) is connected to the substrate pad with a vertical via included in the package substrate (100). However fig. 3 of Min discloses the use of a vertical via (135) which extends through the package substrate (112) to connect a lower conductive structure (121) to an upper surface conductive structure (124). Min discloses that the vertical via (135) provides the benefits of signal loss prevention and increased signal transmission speed (p. 4, paragraph 51). In view of Min, it would therefore be obvious to implement a vertical via in the package substrate to connect the lower substrate pad to the substrate pad in the Park device constructed in view of Disney and Beauchamp.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Disney.
In reference to claim 14, annotated fig. 22A of Park discloses that the left first chip pad is connected to the first chip stack structure (CS1, CS2) and that the right first chip pad is connected to a substrate pad. The right first chip pad is connected to the second chip stack structure (CS3, CS4).
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Park does not disclose that the left second chip pad is also connected to the substrate pad such that the right first chip pad and the left second chip pad are commonly connected to the same substrate pad. However Park discloses that the left second chip pad and the right first chip pad are power/ground pads for the chips (p. 2, paragraph 38). Thus the substrate pad in the above annotated fig. 22A is a power/ground pad for the device. Disney discloses using a commonly connected single pad instead of separate pads for a common signal in order to save package area and cost (p. 2, paragraph 19). In view of Disney, it would therefore be obvious for the first buffer chip (200a) and the second buffer chip (200b) to be commonly connected to the same substrate pad which itself is connected to power/ground in order to save package area and cost. Thus claim 14 is not patentable over Park and Disney.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Min.
With regard to claim 16, fig. 22A of Park discloses upper substrate pads (note unlabeled pads between 200a and 200b) on an upper surface of the package substrate (100) between the first buffer chip (200a) and the second buffer chip (200b). Park does not disclose that the upper substrate pads are shaped such that they extend in the second direction (D1). Although Park does not teach the exact shape of the upper substrate pads as that claimed by the applicant:
The shape, size, dimension differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious. Note In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Therefore this limitation is not patentable over the Park. Fig. 22B of Park discloses a lower substrate pad (note unlabeled pads in direct contact with upper surface of 105) on a lower surface of the package substrate (100). Park does not disclose that the lower substrate pad (note unlabeled pads in direct contact with upper surface of 105) is connected to the upper substrate pad (note unlabeled pads between 200a and 200b) with a vertical via included in the package substrate (100). However fig. 3 of Min discloses the use of a vertical via (135) which extends through the package substrate (112) to connect a lower conductive structure (121) to an upper surface conductive structure (124). Min discloses that the vertical via (135) provides the benefits of signal loss prevention and increased signal transmission speed (p. 4, paragraph 51). In view of Min, it would therefore be obvious to implement a vertical via in the package substrate to connect the lower substrate pad to the upper substrate pad in the Park device.
Allowable Subject Matter
Claims 17-20 are allowed.
Claims 3, 4, 7-11, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a semiconductor package comprising a first package substrate with an internal semiconductor package and a controller chip on it such that the internal semiconductor package comprises a second package substrate with first and second chip stack structures that are formed of stacks of memory chips to the left and right of a first semiconductor chip formed on a left portion of the second package substrate and a second semiconductor chip on a right portion of the second package substrate in combination with the specific pad structures for the first and second semiconductor chips and the second package substrate as described by the applicant in claim 17.
In the examiner’s opinion, it would also not be obvious to implement a semiconductor package comprising a package substrate with first and second chip stack structures that are formed of stacks of memory chips to the left and right of a first semiconductor chip formed on a left portion of the second package substrate and a second semiconductor chip on a right portion of the second package substrate in combination with the specific pad structures, internal circuitry, signal configurations, additional stacked chips, and controller chip connection for the first and second semiconductor chips as described by the applicant in claims 3, 4, 7, 9, 11, and 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
