DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 8/14/24, 9/30/24, 11/1/24, and 2/7/25 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 10, 14 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al., US 2022/0216151.
Regarding claim 1, Kim teaches a device structure (see at least Figures 6 and 7 and abstract), comprising: at least one alternating stack of respective insulating layers and respective electrically conductive layers (insulating layers 120, conductive layers EL), wherein each of the at least one alternating stack comprises respective stepped surfaces located in a staircase region (see Figure 6); at least one retro-stepped dielectric material portion (dielectric layer 210) overlying portions of the at least one alternating stack located in the staircase region; a memory opening (opening for VS1) vertically extending through each layer within the at least one alternating stack; a memory opening fill structure (VS1) located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel ([0108]); and a contact via structure (C2, [0057]) comprising a laterally bulging portion (near the top of C2) in contact with a first electrically conductive layer of the electrically conductive layers within the at least one alternating stack (see Figure 6), an upper portion that vertically extends upward from the laterally bulging portion (see Figure 6) and through the at least one retro-stepped dielectric material portion (id), and a lower portion that vertically extends through second electrically conductive layers of the electrically conductive layers that underlie the first electrically conductive layer (see Figure 6, lower portion of C2), wherein: the second electrically conductive layers are laterally offset from a first cylindrical vertical plane including an outer sidewall of the lower portion of the contact via structure by a first lateral offset distance (offset by dielectric spacers 350); and the first electrically conductive layers are laterally offset from the first cylindrical vertical plane by a second lateral offset distance that is less than the first lateral offset distance (not offset by spacers, so distance is less, see Figure 6).
Regarding claim 10, Kim teaches the invention as explained above regarding claim 1 and further teaches a vertical stack of annular dielectric spacers (Figure 6, spacers 350) laterally surrounding the lower portion of the contact via structures, and laterally surrounded by the second electrically conductive layers (EL, see Figure 6).
Regarding claim 14, Kim teaches the invention as explained above regarding claim 1 and further teaches wherein the first electrically conductive layer has a first thickness in a first portion that laterally surrounds the memory opening fill structure, and has a second thickness that is greater than the first thickness in a second portion that laterally surrounds the contact via structure (see Figure 6, EL layer surrounding bulging portion of C2 is thicker).
Regarding claim 15, Kim teaches a method of forming a device structure (at least Figures 6 and 7), comprising: forming an alternating stack of insulating layers (120) and sacrificial material layers ([0120]) over a substrate (10); forming stepped surfaces by patterning the alternating stack in a staircase region; forming a retro-stepped dielectric material portion over the stepped surfaces ([0119 and 0120]); forming a contact via cavity through the retro-stepped dielectric material portion and a subset of the sacrificial material layers within the alternating stack (for VS1), wherein the subset of the sacrificial material layers comprises a first sacrificial material layer which is a topmost sacrificial material layer of the subset of the sacrificial material layers and further comprises second sacrificial material layers that underlie the first sacrificial material layer ([0120-0121]); replacing an annular portion of the first sacrificial material layer that is proximal to the contact via cavity with a sacrificial fill material spacer; forming a sacrificial contact via structure having a straight sidewall that vertically extends at least from a horizontal plane including a top surface of the retro-stepped dielectric material portion to a horizontal plane including a bottommost surface of the retro-stepped dielectric material portion (VS1, [0128]); replacing the sacrificial material layers with electrically conductive layers such that a first electrically conductive layer of the electrically conductive layers occupies a volume of the sacrificial fill material spacer and a volume of the first sacrificial material layer; and replacing the sacrificial contact via structure with a contact via structure, wherein the contact via structure contacts a cylindrical sidewall of the first electrically conductive layer ([0130-0131]).
Allowable Subject Matter
Claims 2-9, 11-13 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or suggest an outermost surface of the laterally bulging portion is laterally offset from the first cylindrical vertical plane by a third lateral offset distance that is less than the first lateral offset distance.
The prior art further fails to teach or suggest a first isotropic etch process that isotropically etches proximal portions of the first sacrificial material layer and the second sacrificial material layers selectively, wherein first annular recess regions are formed and second annular recess region is formed and the sacrificial dielectric spacer is formed in the second annular recess.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lomeli et al., US 2023/0209819 teaches a microelectronic device having an improved alternating layer stack with improved adhesion, but fails to teach the claimed memory device comprising a stair structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY-ELLEN BOWMAN whose telephone number is (571)270-5383. The examiner can normally be reached Monday-Thursday; 7:00 am-5:00 pm.
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MARY ELLEN BOWMAN
Examiner
Art Unit 2875
/MARY ELLEN BOWMAN/Primary Examiner, Art Unit 2875
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