Prosecution Insights
Last updated: April 19, 2026
Application No. 18/805,140

MEMORY MODULE CAPABLE OF REDUCING POWER CONSUMPTION AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

Non-Final OA §102§112
Filed
Aug 14, 2024
Examiner
BAE, JI H
Art Unit
2176
Tech Center
2100 — Computer Architecture & Software
Assignee
SK Hynix Inc.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
630 granted / 768 resolved
+27.0% vs TC avg
Strong +20% interview lift
Without
With
+20.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
27 currently pending
Career history
795
Total Applications
across all art units

Statute-Specific Performance

§101
7.2%
-32.8% vs TC avg
§103
27.7%
-12.3% vs TC avg
§102
19.4%
-20.6% vs TC avg
§112
36.0%
-4.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 768 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: module controller in claims 1 and 18. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. The specification indicates the following structure as corresponding to the claimed module controller: Fig. 9, module controller 920 comprised of voltage sensing circuit 921 and power control circuit 922. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 4 and 5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 4 recites the limitation “the command signal associated with a standby operation” in line 3. There is insufficient antecedent basis for this limitation in the claim. There is no prior original recitation of a command signal associated with a standby operation as claimed. Claim 1 provides an original recitation for a command signal, but does not recite that the command signal is associated with a standby operation. Claim 5 recites the limitation “the standby operation” in line 3. There is insufficient antecedent basis for this limitation in the claim. There is no prior original recitation of a standby operation in the claim or its parent. Claim 4 provides an original recitation of a standby operation, but it is not a parent of claim 5. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cook et al., U.S. Patent Application Publication No. 2011/0316592. Cook was cited in the IDS filed on 14 August 2024. Regarding claim 1, Cook discloses a memory module comprising: a memory device configured to operate by being applied with a first memory power supply voltage [Fig. 1: Vdd 118 applied to loads 114]; a voltage gating circuit [isolation switch 106] configured to provide one of a first power supply voltage supplied from a power source and a low voltage [Vdd or 0V based on switch state], as the first memory power supply voltage, based on a gating signal [refresh 124 applied to isolation switch 106], the low voltage having a lower level than the first power supply voltage; and a module controller [Fig. 1 and Fig. 2: refresh controller 102] configured to generate the gating signal based on a voltage flag [Fig. 2: refresh 124 output from OR gate 214 is based on SUSPEND signal], and generate a refresh signal [internal refresh signal 124 output from VLFO 202 and inverters 203 provided to OR gate 214] based on a command signal [RST 134 provided to VLFO 202] and a result of sensing a level [para. 0020: “When the electronic device 100 is placed into a suspended mode, the VFLO 202 initiates a flow of current to the capacitor, thereby initiating charging of the capacitor. While the voltage across the capacitor does not exceed the threshold voltage, the VLFO 202 maintains the REFRESH signal 124 in an unasserted state. However, when the voltage across the capacitor exceeds the threshold voltage, the VLFO 202 asserts the REFRESH signal 124 and maintains this signal in the asserted state.”] of the first memory power supply voltage [para. 0022, Fig. 3, 4: capacitor 312 is charged by Vdd, which the same voltage supplied to target devices, i.e., the first memory power supply voltage]. Regarding claim 6, Cook discloses that the memory device operates by being additionally applied with a second memory power supply voltage, the power source provides a second power supply voltage as the second memory power supply voltage, and the second power supply voltage has a lower level than the first power supply voltage [Fig. 1: Vss, i.e., ground]. Allowable Subject Matter Claims 2 and 3 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 4 and 5 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kihara, U.S. Patent No. 9,653,142, discloses an invention that generates a refresh control signal when an input voltage is higher than a specified threshold voltage for an inverter [col. 6, lines 1-8]. Fiscus, U.S. Patent No. 6,714,473, discloses an invention that generates a refresh control signal in response to a voltage level of a first monitor cell rising above a predetermined threshold level [abstract]. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JI H BAE whose telephone number is (571)272-7181. The examiner can normally be reached Tuesday to Friday and every other Monday, 9 am to 6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JI H BAE/Primary Examiner, Art Unit 2176 U.S. Patent and Trademark Office Phone: 571-272-7181 Fax: 571-273-7181 ji.bae@uspto.gov
Read full office action

Prosecution Timeline

Aug 14, 2024
Application Filed
Jan 31, 2026
Non-Final Rejection — §102, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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MEMORY MODULE CAPABLE OF REDUCING POWER CONSUMPTION AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
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MEMORY MODULE CAPABLE OF REDUCING POWER CONSUMPTION AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+20.4%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 768 resolved cases by this examiner. Grant probability derived from career allow rate.

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