Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This action is in response to the remark entered on July 29, 2026.
Claims 1-3, 6, 9, 21-35 pending in the instant application.
Claim 30 is amended.
Claims 4-5, 7-8 & 10-20 are cancelled.
Response to Arguments
All remarks filed 07/29/2026, pages 5-6, are fully considered and moot upon further consideration and new ground(s) of rejections made as outlined in the rejection below.
US Patent 12,713,037 B2
Claims 1-2, 21-24, 26, 27-29, 30, 32-33 & 35 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of US 12,713,037 B2 in view of Lin et al. (US 2022/0150507 A1) (hereinafter Lin), and further in view of Huang et al. (US 2022/0417522 A1) (hereinafter Huang).
Instant – 18/805,374
US 12,713,037 B2
1. A method of video decoding performed at a computing system having memory and one or more processors, the method comprising:
1. A method of video decoding performed at a computing system having memory and one or more processors, the method comprising:
receiving a video bitstream comprising a plurality of blocks;
receiving a video bitstream comprising a plurality of blocks;
deriving a set of motion vectors for a plurality of subblocks of a current block of the plurality of blocks;
deriving a set of subblock motion vectors for a current block of the plurality of blocks;
deriving a set of padded reference subblocks by padding a set of reference samples at a padding unit level for the current block, wherein the padding unit level is based on a subblock size and subblock shape for the plurality of subblocks;
deriving a set of refined motion vectors for the current block using decoder side motion vector refinement that includes a subblock-based bilinear interpolation and a multi-tap interpolation,
deriving a set of refined subblock motion vectors for the current block by applying the optical flow refinement on the set of subblocks of the current block
wherein the multi-tap interpolation uses reference samples from the set of padded reference subblocks; and
reconstructing the current block using the derived set of refined motion vectors.
reconstructing the current block using the set of refined subblock motion vectors.
Although the claims are not identical, they are not patentably distinct from each other because claim 1, and similarly claims 24 & 30 of the instant application differs from claim 1 of the patent in that the instant application includes the limitations of, deriving a set of padded reference subblocks by padding a set of reference samples at a padding unit level for the current block; deriving a set of refined motion vectors for the current block using decoder side motion vector refinement that includes a subblock-based bilinear interpolation and a multi-tap interpolation; wherein the multi-tap interpolation uses reference samples from the set of padded reference subblocks. However, these limitations are known in the art as evidenced by Lin, wherein Paragraphs [0022]-[0025], [0062]-[0066] & Fig. 17, describe padding around the sub-partition reference block of each sub-partition, which means padding is on sub-partition base instead of CU base and Paragraph [0061]-[0065] & [0096] & Figs. 15 & 17, wherein a bi-linear interpolation filter is used to generate the fractional samples for the DMVR search process. After the refined MV is attained with the DMVR search process, a normal 8-tap interpolation filter is applied to generate the final prediction. It would have been obvious to the person of ordinary skill in the art at the time of the invention to modify the instant invention to add the teachings of Lin as above, to improve the coding efficiency as Lin discusses in Paragraph [0013].
Furthermore, the claims are not patentably distinct from each other because claim 1 and similarly claims 24 & 30 of the instant application differs from claim 1 of the patent in that the instant application includes the limitations of, wherein the padding unit level is based on a subblock size and subblock shape for the plurality of subblocks. However, these limitations are known in the art as evidenced by Huang, wherein Paragraph [0056] describes encoding device 104 may partition a superblock and other coding blocks into smaller blocks using square or non-square partitioning. Non-square blocks may include N/2×N, N×N/2, N/4×N, and N×N/4 blocks. It would have been obvious to the person of ordinary skill in the art at the time of the invention to modify the instant invention to add the teachings of Huang as above, providing improvements to decoder side motion vector refinement, such as by providing adaptive bilateral motion vector refinement using selectable search algorithms and associated constraints as Huang describes in Paragraph [0035]-[0039].
Regarding claims 2, 21-24, 26-30, 32-33 & 35, although the claims are not identical, the further limitations would have been obvious for the same reasons of obviousness as set forth in the rejections outlined below with respect to Lin and Huang.
Claims 3, 6, 9, 25, 31 & 34 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of US 12,713,037 B2 in view of Lin et al. (US 2022/0150507 A1) (hereinafter Lin) and Huang et al. (US 2022/0417522 A1) (hereinafter Huang), in view of Xiu et al. (US 2022/0239943 A1) (hereinafter Xiu).
Regarding claims 3, 6, 9, 25, 31 & 34, although the claims are not identical, the further limitations would have been obvious for the same reasons of obviousness as set forth in the rejections outlined below with respect to Xiu.
This is a nonstatutory double patenting rejection
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 21-24, 26, 27-29, 30, 32-33 & 35 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2022/0150507 A1) (hereinafter Lin) in view of Huang et al. (US 2022/0417522 A1) (hereinafter Huang).
Regarding claim 1, Lin discloses a method of video decoding performed at a computing system having memory and one or more processors [Abstract, Paragraph [0097], Fig. 17, Video decoder having one or more processors configured to execute program instructions stored in memory], the method comprising:
receiving a video bitstream comprising a plurality of blocks [Paragraph [0095]-[0096], Fig. 17, Video bitstream input to entropy decoder 1710, comprising current blocks in video];
deriving a set of motion vectors for a current block of the plurality of blocks [Paragraph [0022], [0065], [0096], Fig. 17, Inter Prediction module 1714 deriving list0/list1 motion vectors for bi-prediction, based on MV candidate around initial MVs, as MV0 and MV1];
deriving a set of padded reference subblocks by padding a set of reference samples at a padding unit level for the current block [Paragraph [0062]-[0066], padding around the sub-partition reference block of each sub-partition, which means padding is on sub-partition base instead of CU base];
deriving a set of refined motion vectors for the current block using decoder side motion vector refinement [Paragraph [0022]-[0024], Fig. 17, Using decoder side motion vector refinement from VVC standard, a refined MV is searched around initial MVs in ref picture list L0/L1 to identify MV0’ and MV1’] that includes a subblock-based bilinear interpolation and a multi-tap interpolation. wherein the multi-tap interpolation uses reference samples from the set of padded reference subblocks [Paragraph [0025] & [0061]-[0063], a bi-linear interpolation filter is used to generate the fractional samples for the DMVR search process. After the refined MV is attained with the DMVR search process, a normal 8-tap interpolation filter is applied to generate the final prediction]; and
reconstructing the current block using the derived set of refined motion vectors [Paragraph [0061]-[0065] & [0096], Figs. 15 & 17, padding operation is applied for each WxH sub-partition level after DMVR operation at Inter-prediction module 1714 to produce reconstructed video at REC 1718].
However, Lin does not explicitly disclose deriving a set of motion vectors for a plurality of subblocks of a current block; and wherein the padding unit level is based on a subblock size and subblock shape for the plurality of subblocks;
Huang teaches deriving a set of motion vectors for a plurality of subblocks of a current block [Paragraph [0083], Each sub-block can have a different motion vector in each direction. Therefore, a motion vector is present in a level equal to higher than sub-block], and wherein the padding unit level is based on a subblock size and subblock shape for the plurality of subblocks [Paragraph [0056], Encoding device 104 may partition a superblock and other coding blocks into smaller blocks using square or non-square partitioning. Non-square blocks may include N/2×N, N×N/2, N/4×N, and N×N/4 blocks].
It would have been obvious to the person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method disclosed by Lin to integrate the padding implementation techniques as described in Huang as above, providing improvements to decoder side motion vector refinement, such as by providing adaptive bilateral motion vector refinement using selectable search algorithms and associated constraints (Huang, Paragraph [0035]-[0039]).
Regarding claim 2, Lin and Huang disclose the method of claim 1 and are analyzed as previously discussed with respect to the claim.
Furthermore, Lin discloses wherein the padding unit level corresponds to a square block [Paragraph [0061]-[0065] & [0096], Figs. 13-14, Padding reference block at sub-partition level is a square shape block].
Regarding claim 21, Lin and Huang disclose the method of claim 1 and are analyzed as previously discussed with respect to the claim.
Furthermore, Lin discloses wherein the multi-tap interpolation comprises an 8-tap interpolation [Paragraph [0025] & [0061]-[0063], a normal 8-tap interpolation filter is applied to generate the final prediction].
Regarding claim 22, Lin and Huang disclose the method of claim 1 and are analyzed as previously discussed with respect to the claim.
Furthermore, Lin discloses wherein the padding unit level is smaller than a size of the current block [Paragraph [0026] & [0061]-[0063], When one or both of the width and height of a CU is larger than 16 luma samples, the CU is further partitioned into sub-blocks with one or both of the width and height equal to 16 luma samples].
Regarding claim 23, Lin and Huang disclose the method of claim 1 and are analyzed as previously discussed with respect to the claim.
Furthermore, Lin discloses wherein the subblock-based bilinear interpolation is an initial interpolation of the decoder side motion vector refinement, and the multi-tap interpolation is a final interpolation of the decoder side motion vector refinement [Paragraph [0025] & [0061]-[0063], a bi-linear interpolation filter is used to generate the fractional samples for the DMVR search process. After the refined MV is attained with the DMVR search process, a normal 8-tap interpolation filter is applied to generate the final prediction].
Regarding claims (24 & 26-29), method claims (24 & 26-29) are drawn to the method of video encoding comprising limitations similar and reciprocal to the method of video decoding as claimed in claims (1-2 & 21-23), respectively. Therefore, method claims (24 & 26-29) correspond to method claims (1-2 & 21-23), and are rejected for the same reasons of obviousness as used above.
Furthermore, Lin discloses a method of video encoding performed at a computing system having memory and one or more processors [Abstract, Paragraph [0097]-[0100], A computer-readable medium can include one or more memory devices or chips, according to particular needs. The software can cause the core (2740) and specifically the processors therein (including CPU, GPU, FPGA, and the like) to execute particular processes including methods for encoding].
Regarding claims (30, 32-33 & 35), non-transitory computer-readable storage medium claims (30, 32-33 & 35) are drawn to the non-transitory computer-readable storage medium storing one or more instructions comprising limitations similar and reciprocal to the method of video decoding as claimed in claims (1-2 & 21-22), respectively. Therefore, non-transitory computer-readable storage medium claims (30, 32-33 & 35) correspond to method claims (1-2 & 21-22) and are rejected for the same reasons of obviousness as used above.
Furthermore, Lin discloses of the non-transitory computer-readable storage medium storing one or more instructions that, when executed by a processor, cause a computing system to perform a method [Paragraph [0097]-[0100], A computer-readable medium can include one or more memory devices or chips, according to particular needs. The software can cause the core (2740) and specifically the processors therein (including CPU, GPU, FPGA, and the like) to execute particular processes]; and transmit a video bitstream that comprises encoded information for the current block [Paragraph [0095], Fig. 16, Entropy encoder 1632 generates video bitstream and transmitted to decoder 1700].
Claims 3, 6, 9, 25, 31 & 34 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2022/0150507 A1) (hereinafter Lin) in view of Huang et al. (US 2022/0417522 A1) (hereinafter Huang).
Regarding claim 3, Lin and Huang disclose the method of claim 1 and are analyzed as previously discussed with respect to the claim.
However, Lin does not disclose the particulars of claim 3.
Xiu teaches further discloses wherein the size of the padding unit level is the same as a size of the plurality of reference subblocks [Paragraph [0166]-[0169], Fig. 19, Padding reference block at sub-partition level is 4x4 at the 4x4 padding level unit].
It would have been obvious to the person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method disclosed by Li to integrate the padding implementation techniques as described in Xiu as above, to improve and simplify the existing design to facilitate hardware codec implementations and improve coding efficiency (Xiu, Paragraph [0107]-[0109]).
Regarding claim 6, Lin and Huang disclose the method of claim 1, and are analyzed as previously discussed with respect to the claim.
Furthermore, Lin discloses wherein a size of the padding unit level is signaled in high-level syntax of the video bitstream [Paragraph [0016], The current PU is divided into sub-PUs, where the depth of sub-PU (e.g. 3) is signaled in Sequence Parameter Set (SPS) with a minimum sub-PU size of 4×4 samples.].
It would have been obvious to the person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method disclosed by Li to integrate the padding implementation techniques as described in Xiu as above, to improve and simplify the existing design to facilitate hardware codec implementations and improve coding efficiency (Xiu, Paragraph [0107]-[0109]).
Regarding claim 9, Lin and Huang disclose the method of claim 1 and are analyzed as previously discussed with respect to the claim.
However, Lin does not disclose the particulars of claim 9.
Xiu teaches wherein a delta for the size of the padding unit level is predefined or signaled in high-level syntax of the video bitstream [Paragraph [0166]-[0169], According to the current disclosure, different metrics may be used in determining if the MV difference is small enough to skip the PROF process. In one example, based on the equation (19), the PROF process can be skipped when the sum of the absolute maximal horizontal MV difference and the absolute maximal vertical MV difference is smaller than one predefined threshold, i.e., |Δv x max |+|Δv y max|≤thresh].
It would have been obvious to the person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method disclosed by Li to integrate the padding implementation techniques as described in Xiu as above, to improve and simplify the existing design to facilitate hardware codec implementations and improve coding efficiency (Xiu, Paragraph [0107]-[0109]).
Regarding claim 25, method claim 25 is drawn to the method of video encoding comprising limitations similar and reciprocal to the method of video decoding as claimed in claim 3. Therefore, method claim 25 corresponds to method claim 3 and is rejected for the same reasons of obviousness as used above.
Regarding claims (31 & 34), non-transitory computer-readable storage medium claims (31 & 34) are drawn to the non-transitory computer-readable storage medium storing one or more instructions comprising limitations similar and reciprocal to the method of video decoding as claimed in claims (3 & 6), respectively. Therefore, non-transitory computer-readable storage medium claims (31 & 34) correspond to method claims (3 & 6) and are rejected for the same reasons of obviousness as used above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL CHANG whose telephone number is (571)272-5707. The examiner can normally be reached M-Sa, 12PM - 10 PM.
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/DANIEL CHANG/Primary Examiner, Art Unit 2487
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