Prosecution Insights
Last updated: August 18, 2026
Application No. 18/805,524

METHODS TO CONFIGURE AND ACCESS SCALABLE OBJECT STORES USING KV-SSDS AND HYBRID BACKEND STORAGE TIERS OF KV-SSDS, NVME-SSDS AND OTHER FLASH DEVICES

Final Rejection §102§103
Filed
Aug 14, 2024
Priority
Nov 15, 2017 — provisional 62/586,809 +3 more
Examiner
YU, JAE UN
Art Unit
2138
Tech Center
2100 — Computer Architecture & Software
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
6m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
668 granted / 744 resolved
+34.8% vs TC avg
Moderate +10% lift
Without
With
+9.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
18 currently pending
Career history
763
Total Applications
across all art units

Statute-Specific Performance

§101
5.3%
-34.7% vs TC avg
§103
51.0%
+11.0% vs TC avg
§102
24.6%
-15.4% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 744 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 1. Claims 1-3, 6, 8, 11-13, and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Faibish et al. (US 2007/0260842), “Faibish”. 2. As per claim 1, Faibish discloses one or more processors [a computer including a processor 22, figure 1]; and memory [a computer including a memory 22, figure 1] storing instructions that, when executed by the one or more processors, cause the system to: send, to a first device, a first command requesting metadata [sending metadata request to a primary data mover, paragraph 48]; receive the metadata based on the first command [returning the metadata, paragraph 48]; extract a logical block address and an offset from the metadata [a logical block address and an offset extracted, paragraphs 55 & 107] [The examiner interprets that the metadata already includes the logical bocks address and the offset. Since there is no actual transformation of a data into another, the interpretation is proper]; convert the first command to a second command based on the logical block address and the offset [a command utilizing the extracted logical block address and the offset, paragraph 107]; and send the second command to a second device to access data associated with the metadata [data access based on the metadata, figure 14 & paragraph 8]. 3. As per claim 2, Faibish discloses to send the data to an application, wherein the first command is based on receiving an object storage command from the application [file access request from an application program, paragraph 4] and converting the object storage command to the first command [such request is converted to the metadata request, paragraph 48]. 4. As per claim 3, Faibish discloses wherein: the metadata comprises object storage metadata stored on the first device [the metadata on the primary data mover, paragraph 48], and the data comprises object storage data stored on the second device [the data on the disk array, paragraph 8]. 5. As per claim 6, Faibish discloses wherein the logical block address and the offset indicate where the data is stored on the second device [a command utilizing the extracted logical block address and the offset, paragraph 107]. 6. As per claim 8, Faibish discloses wherein the logical block address and the offset indicate where the data is stored on the second device [a command utilizing the extracted logical block address and the offset, paragraph 107]. 7. As per claims 11-13, and 16-19, the examiner directs the applicant’s attention to the claims rejection above. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 1. Claims 7, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Faibish et al. (US 2007/0260842), “Faibish”, in view of Ahn et al. (US 2017/0139594), “Ahn”. 2. As per claim 7, Faibish discloses the system recited in claim 1. Faibish does not disclose expressly a key-value command and a NVMe command. Ahn discloses such features in paragraph 39. Faibish and Ahn are analogous art because they are from the same field of endeavor of storage device control. Before the effective filing date of the application, it would have been obvious to a person of ordinary skill in the art to modify Faibish by including the key-value translation layer for the NVMe device as taught by Ahn in paragraph 39. The motivation for doing so would have been to reduce they system overhead as expressly taught by Ahn in paragraph 39. 3. As per claims 9 and 10, the examiner directs the applicant’s attention to the claim rejection above. Arguments Concerning Prior Art Rejection The applicant argues that the prior art fails to disclose extracting a logical address and an offset from a metadata. However, Faibish teaches utilizing a metadata for logical/virtual addressing thought the reference. For example, Faibish discloses in paragraph 148 & figure 27, using a metadata for a virtual address allocation, wherein the virtual LU identification (0, 1,…N) can be interpreted as the claimed “logical address” and the block identification of the virtual LU can be interpreted as the claimed “offset”. The examiner strongly suggests the applicant to further elaborate in the claim language what the “extraction” step really is. Further, the applicant argues that the prior art fails to disclose converting the first command to a second command based on the logical address and the offset. Specifically, the applicant asserts that Faibish teaches two separate commands instead of converting a command into another. However, as demonstrated above, Faibish teaches the metadata command associated with the virtual LU identification and virtual LU block identification, and (a second command) using such identifications for allocation/access in paragraph 148 & figure 27. Since the second command relies on the result (the logical address and offset) of the first metadata command, such is interpreted as the claimed “conversion”. Again, the applicant needs to further define what the conversion step actually is in the claim language. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. A. Allowable Subject Matter Claims 4, 5, 14, 15, and 20 are objected to. The closest prior art of record, “Faibish” discloses metadata based addressing in the abstract. The primary reasons for allowance of claims 4, 14, and 20 in the instant application is the combination with the inclusion in these claims that “wherein: a first portion of the metadata is stored on the first device and a second portion of the metadata is stored on a third device, and the first portion of the metadata and the second portion of the metadata are retrieved in parallel based on the first command”. The prior art of record neither anticipates nor renders obvious the above recited combination. The primary reasons for allowance of claims 5 and 15 in the instant application is the combination with the inclusion in these claims that “wherein: a first portion of the data is stored on the second device and a second portion of the data is stored on a fourth device, and the first portion of the data and the second portion of the data are accessed in parallel based on the second command”. The prior art of record neither anticipates nor renders obvious the above recited combination. As allowable subject matter has been indicated, applicant's response must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 C.F.R. § 1.111(b) and § 707.07(a) of the MPEP. B. Claims Rejected Claims 1-3, 6-13, and 16-19 are rejected. C. Direction for Future Remarks Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAE UN YU whose telephone number is (571)272-1133. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAE U YU/Primary Examiner, Art Unit 2138
Read full office action

Prosecution Timeline

Aug 14, 2024
Application Filed
Feb 19, 2026
Non-Final Rejection mailed — §102, §103
Apr 27, 2026
Examiner Interview Summary
Apr 27, 2026
Applicant Interview (Telephonic)
May 06, 2026
Response Filed
Jun 23, 2026
Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12705182
PROCESSING CACHE EVICTIONS IN A DIRECTORY SNOOP FILTER WITH ECAM
1y 5m to grant Granted Aug 11, 2026
Patent 12699654
PACKET PROCESSING DEVICE TO DETERMINE MEMORY TO STORE DATA IN A SERVER ARCHITECTURE AND COMPUTING SYSTEM INCLUDING SAME
4y 1m to grant Granted Aug 04, 2026
Patent 12656962
AUTHENTICATION SERVER, AUTHENTICATION SYSTEM, AND AUTHENTICATION METHOD
1y 6m to grant Granted Jun 16, 2026
Patent 12639223
EMBEDDED CONFIGURABLE ENGINE
2y 3m to grant Granted May 26, 2026
Patent 12640209
MODULATION OF SOURCE VOLTAGE IN NAND-FLASH ARRAY READ
1y 10m to grant Granted May 26, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+9.8%)
2y 6m (~6m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 744 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month