DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 10, 12, 14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cheng et al. (US 20190287864 A1) hereinafter referred to as "Cheng".
Regarding claim 1, Cheng discloses a semiconductor device, comprising: a substrate (Fig. 2, element 102B; ¶: [0040]) including a plurality of active regions (Fig. 2, element 172, 182; ¶: [0039]) extending in a first direction and including first (Fig. 2, element 172; ¶: [0039]) and second (Fig. 2, element 182; ¶: [0039]) active regions spaced apart from each other in a second direction, intersecting the first direction; a plurality of gate structures (Fig. 2, element 202, 204, 206, 212, 214, 216; ¶: [0037, 0054]) extending on the substrate in the second direction, and including a first gate structure (Fig. 2, element 202, 204, 206; ¶: [0037]) intersecting the first active region and a second gate structure (Fig. 2, element 212, 214, 216; ¶: [0054]) intersecting the second active region; on each of the plurality of active regions, a plurality of channel layers (Fig. 2, element 122A, 124A, 126A; ¶: [0036]) spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and surrounded by the gate structure; on one side of each of the plurality of gate structures, a plurality of source/drain regions (Fig. 2, element 1202, 1204, 1206, 1208; ¶: [0036, 0053]) including a first source/drain region (Fig. 2, element 1202; ¶: [0036, 0053]) in a first region in which the first active region is recessed, the first source/drain region connected to the plurality of channel layers on the first active region and having a first conductivity-type (Fig. 2, element 1202; ¶: [0053]), and a second source/drain region (Fig. 2, element 1208; ¶: [0053]) in a second region in which the second active region is recessed, the second source/drain region connected to the plurality of channel layers on the second active region and having a second conductivity-type (Fig. 2, element 1208; ¶: [0053]), different from the first conductivity-type; first internal spacers (Fig. 2, element 1102, 206; ¶: [0036, 0037]) between the first gate structure and the first source/drain region, below each of the plurality of channel layers on the first active region; and second internal spacers (Fig. 2, element 1104; ¶: [0036]) between the second gate structure and the second source/drain region, below each of the plurality of channel layers on the second active region, each of the first internal spacers including a spacer dielectric layer (Fig. 2, element 1102; ¶: [0037]) and a spacer insulating film (Fig. 2, element 206; ¶: [0036]) between the spacer dielectric layer and the gate structure, and a central thickness of each of the first internal spacers in the first direction is greater than a central thickness of each of the second internal spacers in the first direction (Fig. 2, element 1102, 1104; ¶: [0039]).
Regarding claim 10, Cheng further teaches a top thickness of each of the first internal spacers (Fig. 2, element 1102, 206; ¶: [0036, 0037, 0039]) being greater than a top thickness of each of the second internal spacers (Fig. 2, element 1104; ¶: [0036, 0039]).
Regarding claim 12, Cheng further teaches the first internal spacers (Fig. 2, element 1102, 206; ¶: [0036, 0037, 0052]) including at least one of silicon oxynitride and silicon nitride, and the second internal spacers (Fig. 2, element 1104; ¶: [0036, 0052]) including silicon oxide.
Regarding claim 14, Cheng further teaches wherein in at least some of the first internal spacers (), the spacer insulating film surrounds the gate structure between the plurality of channel layers (Fig. 2, element 206; ¶: [0037]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2-9, 11, 15-17, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Lin et al. (US 20230261080 A1) hereinafter referred to as "Lin".
Regarding claim 2, Cheng in view of Lin discloses the semiconductor device of claim 1. Cheng does not disclose at least some of the first internal spacers further including a spacer pile-up film in contact with the first source/drain region, and the spacer pile-up film including a material different from the spacer dielectric layer.
Lin teaches at least some of the first internal spacers further including a spacer pile-up film (Fig. 35A, element 43C; ¶: [0084, 0092]) in contact with the first source/drain region, and the spacer pile-up film including a material different from the spacer dielectric layer (Fig. 35A, element 43B; ¶: [0079, 0092]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a spacer pile-up film that is a different material due to the lower etch rate present with multiple adjacent spacer layers (Lin, ¶: [0092]).
Regarding claim 3, Cheng in view of Lin discloses the semiconductor device of claim 2. Cheng does not disclose the spacer pile-up film extending along a surface of the first source/drain region between the plurality of channel layers.
Lin teaches the spacer pile-up film (Fig. 35A, element 43C; ¶: [0084]) extending along a surface of the first source/drain region between the plurality of channel layers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the spacer pile-up film extend along the source/drain region in order to compensate for the low etch rate that comes with including multiple spacer layers (Lin, ¶: [92]).
Regarding claim 4, Cheng in view of Lin discloses the semiconductor device of claim 2. Cheng does not disclose the spacer dielectric layer being spaced apart from the first source/drain region by the spacer pile-up film.
Lin teaches the spacer dielectric layer being spaced apart from the first source/drain region by the spacer pile-up film (Fig. 35A, element 43C; ¶: [0073, 0084]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a spacer pile-up film to reduce the effect of dishing (Lin, ¶: [0083]).
Regarding claim 5, Cheng in view of Lin discloses the semiconductor device of claim 2. Cheng does not disclose the spacer dielectric layer including silicon oxide, and the spacer pile-up film including silicon nitride.
Lin teaches the spacer dielectric layer (Fig. 35A, element 43B; ¶: [0079]) including silicon oxide, and the spacer pile-up film (Fig. 35A, element 43C; ¶: [0079]) including silicon nitride.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select either silicon oxide or silicon nitride as material and expect a similar result to the spacer insulating layer which can consist of the same material (Lin, ¶: [89]).
Regarding claim 6, Cheng in view of Lin discloses the semiconductor device of claim 5. Cheng does not disclose the spacer insulating film includes silicon nitride or silicon oxynitride.
Lin teaches the spacer insulating film (Fig. 35a, element 43A; ¶: [0092]) includes silicon nitride or silicon oxynitride.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the material of the spacer insulating film silicon oxynitride in an effort to manipulate the atomic percentage of nitrogen to decrease into the inner part of the layer (Lin, ¶: [89]).
Regarding claim 7, Cheng discloses the semiconductor device of claim 1. Cheng does not directly disclose the first conductivity-type being an N-type, and the second conductivity-type being a P-type. However, Cheng does disclose that In-situ doping (ISD) is applied to form doped S/D regions (Fig. 2, element 172, 182; ¶: [0053]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to source drain regions of two different types in order to create the necessary p-n junctions in the active regions (¶: [0053]).
Regarding claim 8, Cheng discloses the semiconductor device of claim 1. Cheng does not disclose at least some of the first and second internal spacers having a concave shape toward the gate structure.
Lin teaches at least some of the first and second internal spacers (Fig. 35A, element 44; ¶: [51]) having a concave shape toward the gate structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the concave spacer layers to prevent damage by etching to subsequently formed source/drain regions (Lin, ¶: [0051]).
Regarding claim 9, Cheng discloses the semiconductor device of claim 1. Cheng does not disclose a central thickness of each of the second internal spacers in the first direction being smaller than a top thickness of each of the second internal spacers in the first direction.
Lin teaches a central thickness of each of the second internal spacers in the first direction being smaller than a top thickness of each of the second internal spacers in the first direction (Fig. 35A, element 44; ¶: [0049, 0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the spacer layers to prevent damage by etching to subsequently formed source/drain regions (Lin, ¶: [0051]).
Regarding claim 11, Cheng discloses the semiconductor device of claim 1. Cheng does not disclose wherein in at least a portion of each of the first internal spacers, the spacer dielectric layer is spaced apart from the gate structure by the spacer insulating film.
Lin teaches wherein in at least a portion of each of the first internal spacers, the spacer dielectric layer is spaced apart from the gate structure by the spacer insulating film (Fig. 35A, element 43A, 43B; ¶: [0079]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use multiple spacer layers in order to reduce the effect of dishing and prevent unwanted etching consequences (Lin, ¶: [0051, 0083]).
Regarding claim 15, Cheng teaches a semiconductor device, comprising: a substrate (Fig. 2, element 102B; ¶: [0040]) including an active region (Fig. 2, element 172; ¶: [0039]) extending in a first direction; a gate structure (Fig. 2, element 202, 204, 206; ¶: [0037]) extending in a second direction intersecting the active region on the substrate; on the active region, a plurality of channel layers (Fig. 2, element 122A, 124A, 126A; ¶: [0036]) spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and surrounded by the gate structure; a source/drain region (Fig. 2, element 1202; ¶: [0036, 0053]) on at least one side of the gate structure and connected to the plurality of channel layers; and internal spacers (Fig. 2, element 1102, 206; ¶: [0036, 0037]) between the plurality of channel layers and separating the gate structure and the source/drain regions, each of the internal spacers including a spacer insulating film (Fig. 2, element 206; ¶: [0036]) in contact with the gate structure. Cheng does not teach a spacer pile-up film in contact with the source/drain region, and a spacer dielectric layer filling a space between the spacer insulating film and the spacer pile-up film, and the spacer dielectric layer including a material different from the spacer pile-up film and the spacer insulating film.
Lin teaches a spacer pile-up film in (Fig. 35A, element 43C; ¶: [0084, 0092]) contact with the source/drain region, and a spacer dielectric layer filling a space between the spacer insulating film and the spacer pile-up film, and the spacer dielectric layer (Fig. 35A, element 43B; ¶: [0079, 0092]) including a material different from the spacer pile-up film and the spacer insulating film.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a spacer pile-up film that is a different material due to the lower etch rate present with multiple adjacent spacer layers (Lin, ¶: [0092]).
Regarding claim 16, Cheng in view of Lin teaches the semiconductor device of claim 15. Cheng does not teach the spacer pile-up film and the spacer insulating film include silicon nitride or silicon oxynitride, and the spacer dielectric layer includes silicon oxide.
Lin teaches the spacer pile-up film (Fig. 35A, element 43C; ¶: [0079]) and the spacer insulating film (Fig. 35a, element 43A; ¶: [0092]) include silicon nitride or silicon oxynitride, and the spacer dielectric layer (Fig. 35A, element 43B; ¶: [0079]) includes silicon oxide.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the material of the spacer insulating film silicon oxynitride in an effort to manipulate the atomic percentage of nitrogen to decrease into the inner part of the layer and select either silicon oxide or silicon nitride as material and expect a similar result to the spacer insulating layer which can consist of the same material (Lin, ¶: [89]).
Regarding claim 17, Cheng in view of Lin teaches the semiconductor device of claim 15. Cheng does not teach each of the internal spacers having a concave shape toward the gate structure.
Lin teaches each of the internal spacers (Fig. 35A, element 44; ¶: [51]) having a concave shape toward the gate structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the concave spacer layers to prevent damage by etching to subsequently formed source/drain regions (Lin, ¶: [0051]).
Regarding claim 19, Cheng teaches a semiconductor device, comprising: a substrate (Fig. 2, element 102B; ¶: [0040]) including a first region and a second region (Fig. 2, element 172, 182; ¶: [0039]); a first active region (Fig. 2, element 172; ¶: [0039]) extending in a first direction, in the first region on the substrate; a second active region (Fig. 2, element 182; ¶: [0039]) extending in the first direction, in the second region on the substrate; a first gate structure (Fig. 2, element 202, 204, 206; ¶: [0037]) extending on the first active region, in a second direction, intersecting the first direction; a second gate structure (Fig. 2, element 212, 214, 216; ¶: [0054]) extending in the second direction on the second active region; on the first and second active regions, a plurality of channel layers (Fig. 2, element 122A, 124A, 126A; ¶: [0036]) spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, and surrounded by the gate structure; on both sides of the first gate structure, a first source/drain region (Fig. 2, element 1202; ¶: [0036, 0053]) in a first region in which the first active region is recessed, the first source/drain region connected to the plurality of channel layers on the first active region and having a first conductivity-type; on both sides of the second gate structure, a second source/drain region (Fig. 2, element 1208; ¶: [0053]) in a second region in which the second active region is recessed, the second source/drain region connected to the plurality of channel layers on the second active region and having a second conductivity-type, different from the first conductivity-type; first internal spacers (Fig. 2, element 1102, 206; ¶: [0036, 0037]) separating the first gate structure and the first source/drain region, below each of the plurality of channel layers on the first active region; and second internal spacers (Fig. 2, element 1104; ¶: [0036]) separating the second gate structure and the second source/drain region, below each of the plurality of channel layers on the second active region. Cheng does not teach a central thickness of each of the first and second internal spacers in the first direction being smaller than a thickness of an upper end of each of the first and second internal spacers.
Lin teaches a central thickness of each of the first and second internal spacers (Fig. 35A, 35B, element 44; ¶: [0049, 0051]) in the first direction being smaller than a thickness of an upper end of each of the first and second internal spacers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the spacer layers to prevent damage by etching to subsequently formed source/drain regions (Lin, ¶: [0051]).
Regarding claim 20, Cheng in view of Lin teaches the semiconductor device of claim 19. Cheng does not directly disclose the first conductivity-type being an N-type, and the second conductivity-type being a P-type. However, Cheng does disclose that In-situ doping (ISD) is applied to form doped S/D regions (Fig. 2, element 172, 182; ¶: [0053]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to source drain regions of two different types in order to create the necessary p-n junctions in the active regions (¶: [0053]).
Allowable Subject Matter
Claims 13 and 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 13 is objected due to being dependent on claim 1
Claim 18 is objected due to being dependent on claim 15
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13, the prior art teaches elements of the claimed invention including but not limited to multiple internal spacers in a concave shape between channel layers. But the prior art when taken alone or in combination cannot be construed as to teaching specific elements of the claimed invention regarding “a central thickness of each of the first internal spacers is 1 nm to 3 nm, and a central thickness of each of the second internal spacers is 0.5 nm to 2 nm”.
Regarding claim 18, the prior art teaches elements of the claimed invention including but not limited to multiple internal spacers in a concave shape between channel layers. But the prior art when taken alone or in combination cannot be construed as to teaching specific elements of the claimed invention regarding “a minimum thickness of each of the internal spacers in the first direction is 1 nm to 3 nm”.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/I.H./Examiner, Art Unit 2899 /LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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