Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of species I in the reply filed on 01/06/2026 is acknowledged. The traversal is on the ground(s) that species restriction was improper. This is found persuasive and species restriction requirement is reversed. Previously withdrawn claims will be examined.
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Okada et al. (US 6249169 and Okada hereinafter.) in view of Xu et al. (US 9479173 B1 and Xu hereinafter.).
Regarding claim 1, Regarding claim 1, Okada discloses [fig. 4] a switching circuit [10a] comprising: an output inverter [11] configured to switch an output signal [out] to either a high-level voltage [n1] or a low-level voltage [n2], at least one stage of a first inverter [15] configured to generate the high-level voltage from a first supply voltage [Vdd] according to a first input signal [in1], at least one stage of a second inverter [16] configured to generate the low-level voltage from a second supply voltage [Vss] according to a second input signal [in2]. Okada does not explicitly disclose at least one stage of a first bias portion configured to lower a voltage fed to a high-side power terminal of the first inverter in each stage by a first bias voltage and to feed a lowered voltage to a low-side power terminal of the first inverter in each stage; and at least one stage of a second bias portion configured to raise a voltage fed to a low-side power terminal of the second inverter in each stage by a second bias voltage and to feed a raised voltage to a high-side power terminal of the second inverter in each stage.
However, Xu discloses at least one stage of a first bias portion [fig. 4b, a first multiplexer 450a and 450b] configured to lower a voltage [Vpg selected as instead of Vcc] fed to a high-side power terminal of the first inverter [voltage fed to a high-side power terminal of a first 210] in each stage by a first bias voltage [450a transition from Vcc to Vpg] and to feed a lowered voltage to a low-side power terminal of [voltage fed to a low-side power terminal] the first inverter in each stage; and at least one stage of a second bias portion [a second and duplicate multiplexer 450a and 450b] configured to raise a voltage [Vss selected instead of Vss] fed to a low-side power terminal of the second inverter [voltage fed to a low-side power terminal of a second 210] in each stage by a second bias voltage [450b transition from Vss to -0.2v] and to feed a raised voltage to a high-side power terminal of the second inverter in each stage. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Okada to include at least one stage of a first bias portion configured to lower a voltage fed to a high-side power terminal of the first inverter in each stage by a first bias voltage and to feed a lowered voltage to a low-side power terminal of the first inverter in each stage; and at least one stage of a second bias portion configured to raise a voltage fed to a low-side power terminal of the second inverter in each stage by a second bias voltage and to feed a raised voltage to a high-side power terminal of the second inverter in each stage as taught by Xu to improve operational speed of an inverting circuit.
Regarding claim 6, Okada in Xu disclose further wherein an input terminal of the output inverter is connected to the low-side power terminal of the first inverter in a final stage [Okada, as shown in fig. 4] and to the high-side power terminal of the second inverter in the final stage [Okada, as shown in fig. 4].
Regarding claim 7, Okada in view of Xu discloses all the features regarding claim 1 as indicated above. Okada in view of Xu discloses further wherein the output inverter [Okada, CMOS inverter circuit 11]. Okada in view of Xu does not explicitly disclose the first and second inverters in each stage are all CMOS inverters. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have inverters be made of CMOS components, such as MOSFETs, since it was known in the art.
Allowable Subject Matter
Claims 2-5 and 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES G YEAMAN whose telephone number is (571)272-5580. The examiner can normally be reached Mon - Fri 954 Schedule.
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/JAMES G YEAMAN/Examiner, Art Unit 2842 /Jessica Han/Supervisory Patent Examiner, Art Unit 2896
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