Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/06/2026 has been entered.
2. This action is response to communication filed on 05/06/2026. Claims 1-3, 5-10, 12-17, 19-21 are pending.
Claim rejections-35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1, 3, 8, 10, 15, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Gray (CN 111935035 A), hereafter Gray’5035 in view of Gray (US 20170220499), hereafter Gray’0499 and further in view of Fernandez et al. (US 20250390648)
Regarding claim 1:
A method, comprising:
algorithmically elaborating (expand) one or more of Network on Chips (NoCs) through a multi- level hierarchical topology composed of instantiations of sub-NoCs and leaf components: (Gray’5035 teaches performance expandable reason, a very large system includes a hierarchical system of interconnection, such as the hierarchical system comprises a plurality of secondary interconnection network and the NOC interconnected to the integrated system. Gray’5035 teaches to connecting the client core to a particular external interface, the NOC may provide an efficient way of interconnecting the various client cores to the second interconnect network and exchanging data with it. An embodiment, for performance hierarchical, very large system may include a hierarchical system of interconnection, such as the hierarchical system comprises a plurality of secondary interconnection network and the NOC interconnected to the integrated system in the integrated system. The hierarchical NOC routers can use the 3D or higher dimensional coordinates to address, for example, the router (x, y, i, j) is the (i, j) router in the secondary NOC found at the global NOC router (x, y) at the global NOC (Gray’5035, page 42).
one or more connectivity definitions: (it would have been obvious to understand connections between NOC, and other networks should be defined. Furthermore, with the similar art, Gray’0499 teaches NOC ring link pipeline registers ([0038]). Gray’0499 also teaches the destination address may comprise bits that describe the desired routing path to take through the routers of the NOC to reach the destination router. In general, a message comprises a description of the destination router sufficient to determine whether the message, as it is traverses a two (or greater) dimensional arrangement of routers (Gray’0499, [0100]). Ideally, Gray’0499 teaching reads on “one or more connectivity definitions” as claimed.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Gray’0499’s ideas into Gray’5035’s system in order to provide an efficient network-on-chip (NoC) design network (see Gray’0499, [0004]-[0005]).
However, Gray’503- Gray’0499 does not teach Network on Chips (NoCs) designs defined using a hardware description language (HDL) through input of a multi-level hierarchical topology.
In similar art, Fernandez the flow includes a NoC netlist . The netlist can contain a list of network connections, or nets, that result from the visually represented NoC design. The netlist can be included in a file that can be downloaded to a user from the CNDE. The NoC netlist can include one or more stubs those can comprise an integration point for a description of the first network initiator, the second network initiator, the first network target, and the second network target. The description can be based on a hardware description language (HDL) (Fernandez [0040]);
wherein the algorithmically elaborating the sub-NoCs and the leaf components comprises combining the hierarchical topology with traffic specifications associated with the NoCs: (the floorplan includes physical information about the NoC topology and NoC sub-topologies: Fernandez [0043]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Fernandez’s ideas into Gray’5035-Gray’0499’s system in order to provide an efficient network-on-chip (NoC) design network (see Fernandez, [0006]-[0007]).
Regarding claim 3:
In addition to the rejection claim 1, Gray’5035-Gray’0499-Fernandez further teaches the sub-NoCs and the leaf components are pre-elaborated: (a very large system includes a hierarchical system of interconnection, such as the hierarchical system comprises a plurality of secondary interconnection network and the NOC interconnected to the integrated system. Gray’5035 teaches to connecting the client core to a particular external interface, the NOC may provide an efficient way of interconnecting the various client cores to the second interconnect network and exchanging data with it. An embodiment, for performance hierarchical, very large system may include a hierarchical system of interconnection, such as the hierarchical system comprises a plurality of secondary interconnection network and the NOC interconnected to the integrated system in the integrated system: Gray’5035, page 42).
Regarding claim 8:
A non-transitory computer-readable storage medium storing instructions for executing a process, comprising:
algorithmically elaborating (expand) one or more of Network on Chips (NoCs) through a multi- level hierarchical topology composed of instantiations of sub-NoCs and leaf components: (Gray teaches performance expandable reason, a very large system includes a hierarchical system of interconnection, such as the hierarchical system comprises a plurality of secondary interconnection network and the NOC interconnected to the integrated system. Gray’5035 teaches to connecting the client core to a particular external interface, the NOC may provide an efficient way of interconnecting the various client cores to the second interconnect network and exchanging data with it. An embodiment, for performance hierarchical, very large system may include a hierarchical system of interconnection, such as the hierarchical system comprises a plurality of secondary interconnection network and the NOC interconnected to the integrated system in the integrated system. The hierarchical NOC routers can use the 3D or higher dimensional coordinates to address, for example, the router (x, y, i, j) is the (i, j) router in the secondary NOC found at the global NOC router (x, y) at the global NOC (page 42).
one or more connectivity definitions: It would have been obvious to understand connections between NOC, and other networks should be defined. Furthermore, with the similar art, Gray’0499 teaches NOC ring link pipeline registers ([0038]). Gray’0499 also teaches the destination address may comprise bits that describe the desired routing path to take through the routers of the NOC to reach the destination router. In general, a message comprises a description of the destination router sufficient to determine whether the message, as it is traverses a two (or greater) dimensional arrangement of routers ([0100]). Ideally, Gray’0499 teaching reads on “one or more connectivity definitions” as claimed.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Gray’0499’s ideas into Gray’5035’s system in order to provide an efficient network-on-chip (NoC) design network (see Gray’0499, [0004]-[0005]).
However, Gray’503- Gray’0499 does not teach Network on Chips (NoCs) designs defined using a hardware description language (HDL) through input of a multi-level hierarchical topology.
In similar art, Fernandez the flow includes a NoC netlist . The netlist can contain a list of network connections, or nets, that result from the visually represented NoC design. The netlist can be included in a file that can be downloaded to a user from the CNDE. The NoC netlist can include one or more stubs those can comprise an integration point for a description of the first network initiator, the second network initiator, the first network target, and the second network target. The description can be based on a hardware description language (HDL) (Fernandez [0040]);
wherein the algorithmically elaborating the sub-NoCs and the leaf components comprises combining the hierarchical topology with traffic specifications associated with the NoCs: (the floorplan includes physical information about the NoC topology and NoC sub-topologies: Fernandez [0043]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Fernandez’s ideas into Gray’5035-Gray’0499’s system in order to provide an efficient network-on-chip (NoC) design network (see Fernandez, [0006]-[0007]).
Regarding claim 10:
In addition to the rejection claim 8, Gray’5035-Gray’0499-Fernandez further teaches the sub-NoCs and the leaf components are pre-elaborated: (a very large system includes a hierarchical system of interconnection, such as the hierarchical system comprises a plurality of secondary interconnection network and the NOC interconnected to the integrated system. Gray’5035 teaches to connecting the client core to a particular external interface, the NOC may provide an efficient way of interconnecting the various client cores to the second interconnect network and exchanging data with it. An embodiment, for performance hierarchical, very large system may include a hierarchical system of interconnection, such as the hierarchical system comprises a plurality of secondary interconnection network and the NOC interconnected to the integrated system in the integrated system: Gray’5035, page 42).
Regarding claim 15
An apparatus, comprising a processor configured to:
algorithmically elaborating (expand) one or more of Network on Chips (NoCs) through a multi- level hierarchical topology composed of instantiations of sub-NoCs and leaf components: (Gray teaches performance expandable reason, a very large system includes a hierarchical system of interconnection, such as the hierarchical system comprises a plurality of secondary interconnection network and the NOC interconnected to the integrated system. Gray’5035 teaches to connecting the client core to a particular external interface, the NOC may provide an efficient way of interconnecting the various client cores to the second interconnect network and exchanging data with it. An embodiment, for performance hierarchical, very large system may include a hierarchical system of interconnection, such as the hierarchical system comprises a plurality of secondary interconnection network and the NOC interconnected to the integrated system in the integrated system. The hierarchical NOC routers can use the 3D or higher dimensional coordinates to address, for example, the router (x, y, i, j) is the (i, j) router in the secondary NOC found at the global NOC router (x, y) at the global NOC (page 42).
one or more connectivity definitions: It would have been obvious to understand connections between NOC, and other networks should be defined. Furthermore, with the similar art, Gray’0499 teaches NOC ring link pipeline registers ([0038]). Gray’0499 also teaches the destination address may comprise bits that describe the desired routing path to take through the routers of the NOC to reach the destination router. In general, a message comprises a description of the destination router sufficient to determine whether the message, as it is traverses a two (or greater) dimensional arrangement of routers ([0100]). Ideally, Gray’0499 teaching reads on “one or more connectivity definitions” as claimed.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Gray’0499’s ideas into Gray’5035’s system in order to provide an efficient network-on-chip (NoC) design network (see Gray’0499, [0004]-[0005]).
However, Gray’503- Gray’0499 does not teach Network on Chips (NoCs) designs defined using a hardware description language (HDL) through input of a multi-level hierarchical topology.
In similar art, Fernandez the flow includes a NoC netlist . The netlist can contain a list of network connections, or nets, that result from the visually represented NoC design. The netlist can be included in a file that can be downloaded to a user from the CNDE. The NoC netlist can include one or more stubs those can comprise an integration point for a description of the first network initiator, the second network initiator, the first network target, and the second network target. The description can be based on a hardware description language (HDL) (Fernandez [0040]);
wherein to algorithmically elaborate the sub-NoCs or the leaf components according to the hierarchical topology, the processor is configured to combine the hierarchical topology with traffic specifications associated with the NoCs: (the floorplan includes physical information about the NoC topology and NoC sub-topologies: Fernandez [0043]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Fernandez’s ideas into Gray’5035-Gray’0499’s system in order to provide an efficient network-on-chip (NoC) design network (see Fernandez, [0006]-[0007]).
Regarding claim 17:
In addition to the rejection claim 15, Gray’5035-Gray’0499-Fernandez further teaches the sub-NoCs and the leaf components are pre-elaborated: (a very large system includes a hierarchical system of interconnection, such as the hierarchical system comprises a plurality of secondary interconnection network and the NOC interconnected to the integrated system. Gray’5035 teaches to connecting the client core to a particular external interface, the NOC may provide an efficient way of interconnecting the various client cores to the second interconnect network and exchanging data with it. An embodiment, for performance hierarchical, very large system may include a hierarchical system of interconnection, such as the hierarchical system comprises a plurality of secondary interconnection network and the NOC interconnected to the integrated system in the integrated system: Gray’5035, page 42).
4. Claims 2, 9, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Gray’5035-Gray’0499-Fernandez in view of Triplet et al. (US 20250168053)
Regarding claim 2:
Gray’5035-Gray’0499-Fernandez discloses the invention substantially as disclosed in claim 1, but does not explicitly teach the hierarchical topology comprises a plurality of root nodes.
In similar art, Triplet teaches facilitating paths through plural of root nodes: (see, Triplet, figure 3 [0087]-[0088]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Triplet’s ideas into Gray’5035-Gray’0499-Fernandez’s system in order to save resources and development time by implying Triplet’s ideas into Gray’5035-Gray’0499-Fernandez’s system.
Regarding claim 9:
Gray’5035-Gray’0499-Fernandez discloses the invention substantially as disclosed in claim 8, but does not explicitly teach the hierarchical topology comprises a plurality of root nodes.
In similar art, Triplet teaches facilitating paths through plural of root nodes: (see, Triplet, figure 3 [0087]-[0088]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Triplet’s ideas into Gray’5035-Gray’0499-Fernandez’s system in order to save resources and development time by implying Triplet’s ideas into Gray’5035-Gray’0499-Fernandez’s system.
Regarding claim 16:
Gray’5035-Gray’0499-Fernandez discloses the invention substantially as disclosed in claim 15, but does not explicitly teach the hierarchical topology comprises a plurality of root nodes.
In similar art, Triplet teaches facilitating paths through plural of root nodes: (see, Triplet, figure 3 [0087]-[0088]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Triplet’s ideas into Gray’5035-Gray’0499-Fernandez’s system in order to save resources and development time by implying Triplet’s ideas into Gray’5035-Gray’0499-Fernandez’s system.
5. Claims 5-6, 12-13, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Gray’5035-Gray’0499-Fernandez in view of Pusuluri et al. (US 20170228481)
Regarding claim 5:
Gray’5035-Gray’0499-Fernandez discloses the invention substantially as disclosed in claim 1, but does not explicitly teach determining a path for each flow in the traffic specifications; and for each path, configuring each component or wire in each path to carry a type of packet for the flow from a prior component of the path to the next component in the path.
In similar art, Pusuluri teaches packets are message transport units for intercommunication between various components. Routing involves identifying a path composed of a set of routers and physical links of the network over which packets are sent from a source to a destination. A NoC interconnect may contain multiple physical networks. Over each physical network, there may exist multiple virtual networks, wherein different message types are transmitted over different virtual networks (see, Pusuluri [0007]; [0012]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Pusuluri’s ideas into Gray’5035-Gray’0499-Fernandez’s system in order to save resources and development time by implying Pusuluri’s ideas into Gray’5035-Gray’0499-Fernandez’s system.
Regarding claim 6:
In addition to the rejection claim 5, Gray’5035-Gray’0499-Fernandez-Pusuluri further teaches the path of the packet through each of the sub-NoCs comprises virtual channel information: (a NoC interconnect may contain multiple physical networks. Over each physical network, there may exist multiple virtual networks, wherein different message types are transmitted over different virtual networks: Pusuluri [0012]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Pusuluri’s ideas into Gray’5035-Gray’0499’s system in order to save resources and development time by implying Pusuluri’s ideas into Gray’5035-Gray’0499- Fernandez’s system.
Regarding claim 12:
Gray’5035-Gray’0499-Fernandez discloses the invention substantially as disclosed in claim 8, but does not explicitly teach determining a path for each flow in the traffic specifications; and for each path, configuring each component or wire in each path to carry a type of packet for the flow from a prior component of the path to the next component in the path.
In similar art, Pusuluri teaches packets are message transport units for intercommunication between various components. Routing involves identifying a path composed of a set of routers and physical links of the network over which packets are sent from a source to a destination. A NoC interconnect may contain multiple physical networks. Over each physical network, there may exist multiple virtual networks, wherein different message types are transmitted over different virtual networks: Pusuluri [0007]; [0012]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Pusuluri’s ideas into Gray’5035-Gray’0499-Fernandez’s system in order to save resources and development time by implying Pusuluri’s ideas into Gray’5035-Gray’0499-Fernandez’s system.
Regarding claim 13:
In addition to the rejection claim 12, Gray’5035-Gray’0499- Fernandez-Pusuluri further teaches the path of the packet through each of the sub-NoCs comprises virtual channel information: (a NoC interconnect may contain multiple physical networks. Over each physical network, there may exist multiple virtual networks, wherein different message types are transmitted over different virtual networks: Pusuluri [0012]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Pusuluri’s ideas into Gray’5035-Gray’0499-Fernandez’s system in order to save resources and development time by implying Pusuluri’s ideas into Gray’5035-Gray’0499-Fernandez’s system.
Regarding claim 19:
Gray’5035-Gray’0499-Fernandez discloses the invention substantially as disclosed in claim 15, but does not explicitly teach determining a path for each flow in the traffic specifications; and for each path, configuring each component or wire in each path to carry a type of packet for the flow from a prior component of the path to the next component in the path.
In similar art, Pusuluri teaches packets are message transport units for intercommunication between various components. Routing involves identifying a path composed of a set of routers and physical links of the network over which packets are sent from a source to a destination. A NoC interconnect may contain multiple physical networks. Over each physical network, there may exist multiple virtual networks, wherein different message types are transmitted over different virtual networks (see, Pusuluri [0007]; [0012]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Pusuluri’s ideas into Gray’5035-Gray’0499-Fernandez’s system in order to save resources and development time by implying Pusuluri’s ideas into Gray’5035-Gray’0499-Fernandez’s system.
Regarding claim 20:
In addition to the rejection claim 19, Gray’5035-Gray’0499- Fernandez-Pusuluri further teaches the path of the packet through each of the sub-NoCs comprises virtual channel information: (a NoC interconnect may contain multiple physical networks. Over each physical network, there may exist multiple virtual networks, wherein different message types are transmitted over different virtual networks: Pusuluri [0012]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Pusuluri’s ideas into Gray’5035-Gray’0499-Fernandez’s system in order to save resources and development time by implying Pusuluri’s ideas into Gray’5035-Gray’0499-Fernandez’s system.
6. Claims 7, 14, 21 are rejected under 35 U.S.C. 103 as being unpatentable over Gray’5035-Gray’0499-Fernandez in view of Boucard et al. (US 20250300930)
Regarding claim 7:
Gray’5035-Gray’0499-Fernandez discloses the invention substantially as disclosed in claim 1, but does not explicitly teach traffic flows of the traffic specifications comprise information defining whether virtual channels or physical channels of the NoCs can be shared or not shared with other ones of the traffic flows.
In similar art, Boucard teaches method for enhancing data communication and computation efficiency in Systems on a Chip (SoC). In one aspect, a system is provided that uses a network on a chip (NOC) to route communications between chip components using a plurality of network interfaces linked by shared data connections. The system may be configured to route communications via multiple virtual channels along the shared connections, with credit restrictions for the channels. Additionally, the system may support mechanisms for maintaining both private and shared credit balances for these virtual channels (Boucard abstract).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Boucard’s ideas into Gray’5035-Gray’0499-Fernandez’’s system in order to save resources and development time by implying Boucard’s ideas into Gray’5035-Gray’0499-Fernandez’s system.
Regarding claim 14:
Gray’5035-Gray’0499- Fernandez discloses the invention substantially as disclosed in claim 8, but does not explicitly teach traffic flows of the traffic specifications comprise information defining whether virtual channels or physical channels of the NoCs can be shared or not shared with other ones of the traffic flows.
In similar art, Boucard teaches method for enhancing data communication and computation efficiency in Systems on a Chip (SoC). In one aspect, a system is provided that uses a network on a chip (NOC) to route communications between chip components using a plurality of network interfaces linked by shared data connections. The system may be configured to route communications via multiple virtual channels along the shared connections, with credit restrictions for the channels. Additionally, the system may support mechanisms for maintaining both private and shared credit balances for these virtual channels (Boucard abstract).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Boucard’s ideas into Gray’5035-Gray’0499-Pusuluri’s system in order to save resources and development time by implying Boucard’s ideas into Gray’5035-Gray’0499-Fernandez’s system.
Regarding claim 21:
Gray’5035-Gray’0499-Fernandez discloses the invention substantially as disclosed in claim 15, but does not explicitly teach traffic flows of the traffic specifications comprise information defining whether virtual channels or physical channels of the NoCs can be shared or not shared with other ones of the traffic flows.
In similar art, Boucard teaches method for enhancing data communication and computation efficiency in Systems on a Chip (SoC). In one aspect, a system is provided that uses a network on a chip (NOC) to route communications between chip components using a plurality of network interfaces linked by shared data connections. The system may be configured to route communications via multiple virtual channels along the shared connections, with credit restrictions for the channels. Additionally, the system may support mechanisms for maintaining both private and shared credit balances for these virtual channels (Boucard abstract).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Boucard’s ideas into Gray’5035-Gray’0499- Fernandez’s system in order to save resources and development time by implying Boucard’s ideas into Gray’5035-Gray’0499- Fernandez’s.
Conclusions
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAN DAI T TRUONG whose telephone number is (571)272-7959. The examiner can normally be reached Monday-Friday 7:00 Am to 3:00 PM.
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/LAN DAI T TRUONG/ Primary Examiner, Art Unit 2444
Prosecution Insights