DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 5, and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP2009176771.
With respect to claim 1, JP ‘771 discloses a multilayer ceramic electronic device (see abstract) comprising: a multilayer structure (see abstract) having a substantially rectangular parallelepiped shape in which each of a plurality of internal electrode layers and each of a plurality of dielectric layers are alternately stacked; and a pair of external electrodes that respectively cover a pair of facing end surfaces of the multilayer structure, and are alternately connected to the plurality of internal electrode layers along a stacking direction of the multilayer structure (see paragraph [0021]), wherein, among four surfaces of the multilayer structure excluding the pair of end surfaces, a surface roughness of at least one of a pair of first surfaces that face each other in the stacking direction is smaller than a surface roughness of at least one of a pair of second surfaces that face each other in an orthogonal direction approximately orthogonal to a facing direction in which the pair of end surfaces face each other and the stacking directions (see paragraphs [0033] and [0034]).
With respect to claim 4, JP ‘771 discloses that a difference between a surface roughness of at least one of the pair of first surfaces and a surface roughness of the pair of second surfaces is 0.151 μm or less. See paragraph [0034].
With respect to claim 5, JP ‘771 discloses that a difference between a surface roughness of at least one of the pair of first surfaces and a surface roughness of the pair of second surfaces is 0.025 μm or more. See paragraph [0034].
With respect to claim 7, JP ‘771 discloses that the multilayer ceramic electronic device is a multilayer ceramic capacitor. See paragraph [0020].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over JP2009176771 in view of Fukuda et al. (US Pat. App. Pub. No. 2022/0020534).
With respect to claim 2, JP ‘771 fails to explicitly teach that a length of the stacking direction of the multilayer structure is shorter than a length of the facing direction and the orthogonal direction of the multilayer structure.
Fukuda, on the other hand, teaches that a length of the stacking direction of the multilayer structure is shorter than a length of the facing direction and the orthogonal direction of the multilayer structure. See paragraph [0028]. Such an arrangement is well known in the art as a design choice for a multilayer capacitor. See paragraph [0028].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the application, to modify JP ‘771, as taught by Fukuda, as a design choice for a multilayer capacitor.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over JP2009176771 in view of Sato (US Pat. App. Pub. No. 2020/0066455).
With respect to claim 3, JP ‘771 fails to explicitly teach that a length of the stacking direction of the multilayer structure is larger than a length of the orthogonal direction of the multilayer structure.
Sato, on the other hand, teaches that a length of the stacking direction of the multilayer structure is larger than a length of the orthogonal direction of the multilayer structure. See paragraph [0091]. Such an arrangement results in an improvement in the handling of mountability. See paragraph [0091].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the application, to modify JP ‘771, as taught by Sato, to improve the handing of mountability for a multilayer capacitor.
Claims 8-10 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over JP2009176771 in view of WO 2022/168446.
With respect to claim 8, JP ‘771 teaches a manufacturing method of a multilayer ceramic electronic device (see FIGS. 6 and 7) comprising: stacking a plurality of green sheets, each having an internal electrode layer formed on a surface thereof (see paragraphs [0039]-[0040]); cutting the plurality of green sheets along the stacking direction with a blade so as to divide the plurality of green sheets into a plurality of multilayer structures having a substantially rectangular parallelepiped shape (see paragraph [0042]); and forming a pair of external electrodes so as to cover a pair of facing end surfaces of the multilayer structure and so as to be alternately connected to the internal electrode layers along the stacking direction (see paragraph [0052]), wherein, in the crimping, among four surfaces of the multilayer structure excluding the pair of end surfaces, a surface roughness of a surface of the pressing member contacting at least one of a pair of first surfaces facing each other in the stacking direction is set so that a surface roughness of at least one of the pair of first surfaces is smaller than a surface roughness of at least one of a pair of second surfaces adjacent to the pair of first surfaces (see paragraphs [0033] and [0034]).
JP ‘771 fails to teach crimping the plurality of green sheets in a stacking direction with a pressing member.
WO ‘446 teaches crimping the plurality of green sheets in a stacking direction with a pressing member. See paragraph [0084]. Such an arrangement results in chip-shaped unfired laminates. See paragraph [0084].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the application, to modify JP ‘771, as taught by WO ‘446, in order to produce chip-shaped unfired laminates.
With respect to claim 9, the combined teachings of JP ‘771 and WO ‘446 teach that a difference between the surface roughness of at least one of the pair of first surfaces and the surface roughness of the pair of second surfaces is set to 0.151 μm or less. See JP ‘771, paragraph [0034].
With respect to claim 10, the combined teachings of JP ‘771 and WO ‘446 teach that a difference between the surface roughness of at least one of the pair of first surfaces and the surface roughness of the pair of second surfaces is set to be 0.025 μm or more. See JP ‘771, paragraph [0034].
With respect to claim 12, JP ‘771 teaches a manufacturing method of a multilayer ceramic electronic device (see FIGS. 6 and 7) comprising: stacking a plurality of green sheets, each having an internal electrode layer formed on a surface thereof(see paragraphs [0039]-[0040]); cutting the plurality of green sheets along the stacking direction with a blade so as to divide the plurality of green sheets into a plurality of multilayer structures having a substantially rectangular parallelepiped shape (see paragraph [0042]); and forming a pair of external electrodes so as to cover a pair of facing end surfaces of the multilayer structure and so as to be alternately connected to the internal electrode layers along the stacking direction (see paragraph [0052]), wherein, in the cutting, among four surfaces of the multilayer structure excluding the pair of end surfaces, a cutting edge of the blade is formed with irregularities so that a surface roughness of at least one of a pair of first surfaces facing each other in the stacking direction is smaller than a surface roughness of at least one of a pair of second surfaces adjacent to the pair of first surfaces (see paragraphs [0033] and [0034]).
JP ‘771 fails to teach crimping the plurality of green sheets in a stacking direction with a pressing member.
WO ‘446 teaches crimping the plurality of green sheets in a stacking direction with a pressing member. See paragraph [0084]. Such an arrangement results in chip-shaped unfired laminates. See paragraph [0084].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the application, to modify JP ‘771, as taught by WO ‘446, in order to produce chip-shaped unfired laminates.
With respect to claim 13, the combined teachings of JP ‘771 and WO ‘446 teach that a difference between the surface roughness of at least one of the pair of first surfaces and the surface roughness of the pair of second surfaces is set to 0.151 μm or less. See JP ‘771, paragraph [0034].
With respect to claim 14, the combined teachings of JP ‘771 and WO ‘446 teach that a difference between the surface roughness of at least one of the pair of first surfaces and the surface roughness of the pair of second surfaces is set to be 0.025 μm or more. See JP ‘771, paragraph [0034].
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over JP2009176771 in view of Hattori et al. (US Pat. App. Pub. No. 2017/0339792).
With respect to claim 16, JP ‘771 teaches a multilayer ceramic electronic device (see abstract), wherein the multilayer ceramic capacitor comprises: a multilayer structure (see abstract) having a substantially rectangular parallelepiped shape in which each of a plurality of internal electrode layers and each of a plurality of dielectric layers are alternately stacked (see paragraph [0021]); and a pair of external electrodes that respectively cover a pair of facing end surfaces of the multilayer structure, and are alternately connected to the plurality of internal electrode layers along a stacking direction of the multilayer structure (see paragraph [0021]), wherein, among four surfaces of the multilayer structure excluding the pair of end surfaces, a surface roughness of a first surface of the multilayer structure facing the circuit board is smaller than a surface roughness of at least one of a pair of second surfaces adjacent to the first surface (see paragraphs [0033] and [0034]).
JP ‘771 fails to teach a circuit board and that the multilayer ceramic electronic device is covered with a mold material and mounted on the circuit board.
Hattori, on the other hand, teaches that a circuit board and that the multilayer ceramic electronic device is covered with a mold material and mounted on the circuit board. See paragraph [0014]. Such an arrangement results in the reduction/prevention of vibrations. See paragraph [0014].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the application, to modify JP ‘771, as taught by Hattori, in order to reduce vibrations.
Allowable Subject Matter
Claims 6, 11, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: with respect to claims 6, 11, and 15, the prior art fails to teach the range of roughness for the first and second surfaces when taken in conjunction with one another, and further, in conjunction with the limitations of the respective base claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DION R FERGUSON whose telephone number is (571)270-7566. The examiner can normally be reached Monday-Friday, 5:30 a.m. - 4:00 p.m..
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/DION R. FERGUSON/Primary Examiner, Art Unit 2848