DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 11 and 13 recites the limitation "CSE". There is insufficient antecedent basis for this limitation in the claim. Claim 12 depends on Claim 1 and inherits the deficiency.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim(s) 1 and 16 recite(s):
A method for mapping a quantum program code to a multi-core quantum computing system, comprising: partitioning code into code segments;
identifying, from the code segments, a first group (Gc) comprising at least parts of possible contiguous sequences of the code segments;
identifying a second group (Gnc) comprising at least part of possible non-overlapping combinations of Gc members;
converting each Gc member to a corresponding graph group (Ggc);
mapping logical qubits contained in each Gc member to different physical cores;
generating a respective group of solver results (Gsc), wherein each Gsc corresponds to a respective Gc member and to its corresponding contiguous code part comprising physical qubits;
determining an amount of inter-operations (Asc) related to the contiguous code part corresponding to a respective Gsc;
determining a group of inter-operation amounts (Gamnt) based on the Asc;
and determining an optimal compiled code structure having a smallest amount of Gamnt members.
Step 1: are the claims to a process, machine, manufacture, or a composition of matter?
Yes. Claim 1 is a method
Yes. Claim 16 is a manufacture
Step 2A, Prong I; Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The limitation of "partition", as drafted in #1 above, under its broadest reasonable interpretation, covers performance of the mind, but for generic computer parts. That is, other than reciting "a multi-core quantum computing system" or "a processor", nothing in the claim element precludes the step from being performed by a person on paper.
The limitation of "identifying", as drafted in #2-3 above, under its broadest reasonable interpretation, covers performance of the mind, but for generic computer parts. That is, other than reciting "a multi-core quantum computing system" or "a processor", nothing in the claim element precludes the step from being performed by a person on paper.
The limitation of "converting", as drafted in #4 above, under its broadest reasonable interpretation, covers performance of the mind, but for generic computer parts. That is, other than reciting "a multi-core quantum computing system" or "a processor", nothing in the claim element precludes the step from being performed by a person on paper.
The limitation of "mapping", as drafted in #5 above, under its broadest reasonable interpretation, covers performance of the mind, but for generic computer parts. That is, other than reciting "a multi-core quantum computing system" or "a processor", nothing in the claim element precludes the step from being performed by a person on paper.
The limitation of "generating", as drafted in #6 above, under its broadest reasonable interpretation, covers performance of the mind, but for generic computer parts. That is, other than reciting "a multi-core quantum computing system" or "a processor", nothing in the claim element precludes the step from being performed by a person on paper.
The limitation of "determining", as drafted in #7-9 above, under its broadest reasonable interpretation, covers performance of the mind, but for generic computer parts. That is, other than reciting "a multi-core quantum computing system" or "a processor", nothing in the claim element precludes the step from being performed by a person on paper.
Step 2A Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
Additionally, the claims recite the following additional element:
multi-core quantum computing system,
a non-transitory computer readable medium,
a processor
The element that is recited in the claims are stated at a high level of generality (i.e. as a generic processor performing a generic computer function) such that it amounts no more than mere instructions to apply the exception using generic computer component. See the MPEP §§ 2106.05(f). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limitation on practicing the abstract idea(s).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because mere instructions to apply an exception using generic computer components cannot provide the inventive step.
Claim(s) 2 recite(s):
further comprising remapping logical qubits to physical qubits such that cores having high latency physical connections are involved with fewer inter-operations per core relative to other cores.
Step 1: are the claims to a process, machine, manufacture, or a composition of matter?
Yes. Claim 2 is a method
Step 2A, Prong I; Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
Step 2A Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The "remapping" limitation in #10 above. As claimed and under BRI, is an additional element that is mere instructions to apply an exception. For example, "remapping" in the context of this claim encompasses merely scheduling bits to their physical components. See in the MPEP §§2106.05(f).
Additionally, the claims recite the following additional element:
physical qubits
cores
The element that is recited in the claims are stated at a high level of generality (i.e. as a generic processor performing a generic computer function) such that it amounts no more than mere instructions to apply the exception using generic computer component. See the MPEP §§ 2106.05(f). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limitation on practicing the abstract idea(s).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because mere instructions to apply an exception using generic computer components cannot provide the inventive step.
Claim(s) 3 and 17 recite(s):
further comprising segmenting the code to two or more segments based on identifying code characteristics between adjacent segments.
Step 1: are the claims to a process, machine, manufacture, or a composition of matter?
Yes. Claim 3 is a method
Yes. Claim 17 is a manufacture
Step 2A, Prong I; Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The limitation of "segmenting", as drafted in #11 above, under its broadest reasonable interpretation, covers performance of the mind, but for generic computer parts. That is, other than reciting "multi-core quantum computing system" or "a non-transitory computer readable medium", nothing in the claim element precludes the step from being performed by a person on paper.
Step 2A Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
Additionally, the claims recite the following additional element:
computer readable medium
The element that is recited in the claims are stated at a high level of generality (i.e. as a generic processor performing a generic computer function) such that it amounts no more than mere instructions to apply the exception using generic computer component. See the MPEP §§ 2106.05(f). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limitation on practicing the abstract idea(s).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because mere instructions to apply an exception using generic computer components cannot provide the inventive step.
Claim(s) 4 and 18 recite(s):
wherein each identified group has a minimum length difference in regards to inter-qubit logical operations.
Step 1: are the claims to a process, machine, manufacture, or a composition of matter?
Yes. Claim 4 is a method
Yes. Claim 18 is a manufacture
Step 2A, Prong I; Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
Step 2A Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The limitation in #12 above. As claimed and under BRI, is an additional element that is mere instructions to apply an exception. For example, "each identified group has a minimum length difference" in the context of this claim encompasses merely setting a minimum length for code segments. See in the MPEP §§2106.05(f).
Additionally, the claims recite the following additional element:
a computer readable medium
The element that is recited in the claims are stated at a high level of generality (i.e. as a generic processor performing a generic computer function) such that it amounts no more than mere instructions to apply the exception using generic computer component. See the MPEP §§ 2106.05(f). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limitation on practicing the abstract idea(s).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because mere instructions to apply an exception using generic computer components cannot provide the inventive step.
Claim(s) 5 recite(s):
wherein at least part of the code segments are predetermined according to limiting qubit distribution in a segment by a ratio between a number of different qubits in a segment to a total number of inter-qubit operations not being greater than a predetermined threshold.
Step 1: are the claims to a process, machine, manufacture, or a composition of matter?
Yes. Claim 5 is a method Yes. Claim 19 is a manufacture
Step 2A, Prong I; Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
Step 2A Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The limitation in #13 above. As claimed and under BRI, is an additional element that is mere instructions to apply an exception. For example, "part of the code segments are predetermined" in the context of this claim encompasses merely partitioning to a threshold. See in the MPEP §§2106.05(f).
Additionally, the claims recite the following additional element:
a computer readable medium
The element that is recited in the claims are stated at a high level of generality (i.e. as a generic processor performing a generic computer function) such that it amounts no more than mere instructions to apply the exception using generic computer component. See the MPEP §§ 2106.05(f). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limitation on practicing the abstract idea(s).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because mere instructions to apply an exception using generic computer components cannot provide the inventive step.
Claim(s) 6 recite(s):
further comprising identifying the second group based on a minimum length difference between chosen combinations.
Step 1: are the claims to a process, machine, manufacture, or a composition of matter?
Yes. Claim 6 is a method
Step 2A, Prong I; Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The limitation of "identifying", as drafted in #14 above, under its broadest reasonable interpretation, covers performance of the mind, but for generic computer parts. That is, other than reciting "a multi-core quantum computing system", nothing in the claim element precludes the step from being performed by a person one paper.
Step 2A Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because mere instructions to apply an exception using generic computer components cannot provide the inventive step.
Claim(s) 7 recite(s):
wherein converting Gc members to a respective graph group comprises: associating each logical qubit contained in the contiguous code part constituting a converted Gc member with a different vertex in the graph,
and associating each inter-qubit operation in the converted Gc member with a different edge between a pair of vertices corresponding to that operation
Step 1: are the claims to a process, machine, manufacture, or a composition of matter?
Yes. Claim 7 is a method
Step 2A, Prong I; Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
Step 2A Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The "associating" limitation in #15-16 above. As claimed and under BRI, is an additional element that is mere instructions to apply an exception. For example, "associating" in the context of this claim encompasses merely assigning computing elements to a graph. See in the MPEP §§2106.05(f).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because mere instructions to apply an exception using generic computer components cannot provide the inventive step.
Claim(s) 8 recite(s):
wherein mapping the logical qubits further comprises partitioning graph vertices into exclusive groups representing system cores such that groups number and magnitudes are constrained by a number of the system cores and a number of physical qubits within each core respectively while minimizing a total amount of resulting inter-group edges, which correspond to an amount of operations between different cores.
Step 1: are the claims to a process, machine, manufacture, or a composition of matter?
Yes. Claim 8 is a method
Step 2A, Prong I; Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The limitation, as drafted in #17 above, under its broadest reasonable interpretation, covers performance of the mind, but for generic computer parts. That is, other than reciting "a multi-core quantum computing system", nothing in the claim element precludes the step from being performed by a person on paper.
Step 2A Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
Additionally, the claims recite the following additional element:
System cores
The element that is recited in the claims are stated at a high level of generality (i.e. as a generic processor performing a generic computer function) such that it amounts no more than mere instructions to apply the exception using generic computer component. See the MPEP §§ 2106.05(f). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limitation on practicing the abstract idea(s).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because mere instructions to apply an exception using generic computer components cannot provide the inventive step.
Claim(s) 9 and 20 recite(s):
wherein the inter-operations between different cores needed to transfer qubits comprise qubit teleportation.
Step 1: are the claims to a process, machine, manufacture, or a composition of matter?
Yes. Claim 9 is a method Yes. Claim 20 is a manufacture
Step 2A, Prong I; Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
Step 2A Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The limitations in #18 above, as claimed and under BRI, is an additional element that is insignificant extra-solution activity. For example, "transfer qubits comprise qubit transportation" in the context of this claim encompasses mere data transmission. See in the MPEP §§ 2106.05(g).
Additionally, the claims recite the following additional element:
a computer readable medium
cores
The element that is recited in the claims are stated at a high level of generality (i.e. as a generic processor performing a generic computer function) such that it amounts no more than mere instructions to apply the exception using generic computer component. See the MPEP §§ 2106.05(f). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limitation on practicing the abstract idea(s).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because mere instructions to apply an exception using generic computer components cannot provide the inventive step.
Additionally, with regards to #18 above, per MPEP 2106.05(d)(ll), the courts have recognized the following computer function(s) as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information);
Claim(s) 10 recite(s):
wherein determining the group of inter-operation amounts further comprises, when the Gnc member is an entire code segment, determining a corresponding group of inter-operation amounts (Gamnt) as the amount of inter-operations (Asc) associated with the Gnc member (Gse) corresponding to the entire code segment.
Step 1: are the claims to a process, machine, manufacture, or a composition of matter?
Yes. Claim 10 is a method
Step 2A, Prong I; Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The limitation of "determining", as drafted in #19 above, under its broadest reasonable interpretation, covers performance of the mind, but for generic computer parts. That is, other than reciting "multi-core quantum computing system", nothing in the claim element precludes the step from being performed by a person.
Step 2A Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because mere instructions to apply an exception using generic computer components cannot provide the inventive step.
Claim(s) 11 recite(s):
wherein determining the group of inter-operation amounts further comprises: for any Gnc member that is not an entire code segment, determining an associated Gamnt member by summing Asc amounts associated with all the Gsc members corresponding to the any Gnc member,
and based on a determination that there are code parts outside those Gsc members, for the code parts outside those Gsc members, the determined Gamnt further includes an amount of all Cse inter-operations belonging to the code parts outside those Gsc members.
Step 1: are the claims to a process, machine, manufacture, or a composition of matter?
Yes. Claim 11 is a method
Step 2A, Prong I; Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The limitation of "determining", as drafted in #20 above, under its broadest reasonable interpretation, covers performance of the mind, but for generic computer parts. That is, other than reciting "a multi-core quantum computing system", nothing in the claim element precludes the step from being performed by a person.
Step 2A Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The "based on a determination" limitation in #21 above. As claimed and under BRI, is an additional element that is mere instructions to apply an exception. For example, "the determined Gamnt further includes an amount..” in the context of this claim encompasses merely associating values with other amounts. See in the MPEP §§2106.05(f).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because mere instructions to apply an exception using generic computer components cannot provide the inventive step.
Claim(s) 12 recite(s):
wherein determining the group of inter-operation amounts further comprises, for any Gnc member that is not the entire code segment, determining the associated Gamnt member by applying a penalty for code transitions between Gsc members,
wherein the penalty associated with each transition is determined as the amount of inter-operations needed to transfer qubits between codes.
Step 1: are the claims to a process, machine, manufacture, or a composition of matter?
Yes. Claim 12 is a method
Step 2A, Prong I; Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The limitation of "determining" and "determined", as drafted in #22-23 above, under its broadest reasonable interpretation, covers performance of the mind, but for generic computer parts. That is, other than reciting "a multi-core quantum computing system", nothing in the claim element precludes the step from being performed by a person.
Step 2A Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because mere instructions to apply an exception using generic computer components cannot provide the inventive step.
Claim(s) 13 recite(s):
determining the optimal compiled code structure by: selecting a Gnc member which has a minimum Gsc member;
expressing the code in physical qubit terms according to the Gsc members corresponding to the selected Gnc member and the Cse code parts outside;
and adding inter-operations for transferring qubits between cores to the code.
Step 1: are the claims to a process, machine, manufacture, or a composition of matter?
Yes. Claim 13 is a method
Step 2A, Prong I; Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The limitation of "selecting", as drafted in #24 above, under its broadest reasonable interpretation, covers performance of the mind, but for generic computer parts. That is, other than reciting "a multi-core quantum computing system", nothing in the claim element precludes the step from being performed by a person.
Step 2A Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
The "expressing" limitation in #25 above. As claimed and under BRI, is an additional element that is mere instructions to apply an exception. For example, "expressing the code in physical qubits terms" in the context of this claim encompasses merely showing data in a different format. See in the MPEP §§2106.05(f).
The "adding inter-operations" limitations in #26 above, as claimed and under BRI, is an additional element that is insignificant extra-solution activity. For example, "transferring qubits between cores" in the context of this claim encompasses mere data transmission. See in the MPEP §§ 2106.05(g).
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because mere instructions to apply an exception using generic computer components cannot provide the inventive step.
Additionally, with regards to #26 above, per MPEP 2106.05(d)(ll), the courts have recognized the following computer function(s) as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity:
Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information);
Claim(s) 14 recite(s):
determining the amount of inter-operation amounts (Asc) is based on weighting that is associated with edges of a solver processed graphs.
Step 1: are the claims to a process, machine, manufacture, or a composition of matter?
Yes. Claim 14 is a method
Step 2A, Prong I; Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The limitation of "determining", as drafted in #27 above, under its broadest reasonable interpretation, covers performance of the mind, but for generic computer parts. That is, other than reciting "a multi-core quantum computing system", nothing in the claim element precludes the step from being performed by a person on paper.
Step 2A Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because mere instructions to apply an exception using generic computer components cannot provide the inventive step.
Claim(s) 15 recite(s):
determining the Gamnt members by using weighted sums of inter-operations comprising at least associated qubit transfer operations.
Step 1: are the claims to a process, machine, manufacture, or a composition of matter?
Y
Step 2A, Prong I; Does the claim recite an abstract idea, law of nature, or natural phenomenon?
Yes: (an) abstract idea(s).
The limitation of "determining", as drafted in #28 above, under its broadest reasonable interpretation, covers performance of the mind, but for generic computer parts. That is, other than reciting "a multi-core quantum computing system", nothing in the claim element precludes the step from being performed by a person.
Step 2A Prong II: Does the claim recite additional elements that integrate the judicial exception into a practical application?
No.
Step 2B: Does the claim recite additional elements that amount to significantly more than the judicial exception?
No.
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because mere instructions to apply an exception using generic computer components cannot provide the inventive step.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-8, and 10-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210334081 A1 (Hereinafter referred to as Chong) in view of ‘Automated Distribution of Quantum Circuits via Hypergraph Partitioning’ (Hereinafter referred to as Andres-Martinez).
Regarding claim 1, Chong teaches:
A method for mapping a quantum program code to a multi-core quantum computing system, comprising: partitioning code into code segments (Para. [9], Chong shows "The method includes receiving a quantum program from a user. The quantum program defines a plurality of instructions in a source language. The method also includes compiling the quantum program into logical assembly instructions in an intermediate language. The method further includes aggregating the logical assembly instructions together into a plurality of logical block of instructions." Examiner notes that compiling the code into assembly instructions partitions the quantum program to translate into the intermediate language. The assembly instructions can represent the code segments.);
identifying, from the code segments, a first group (Gc) comprising at least parts of possible contiguous sequences of the code segments (Para. [9], Chong shows "The method includes receiving a quantum program from a user. The quantum program defines a plurality of instructions in a source language. The method also includes compiling the quantum program into logical assembly instructions in an intermediate language. The method further includes aggregating the logical assembly instructions together into a plurality of logical block of instructions." Examiner notes that the citation above shows grouping the compiled assembly instructions into blocks of instructions, which can be considered groups of contiguous code segments.);
identifying a second group (Gnc) comprising at least part of possible non-overlapping combinations of Gc members (Par. [20], Chong shows "the compilation engine provides a compilation framework that both segments the larger problem of scheduling operations on so many qubits into multiple smaller problems (e.g., groupings of qubits and subsets of the program instructions) as well as optimizes those groupings to foster parallelism and to address certain mismatches between the logical instructions of the compilation and the physical constraints of various types of quantum processors. More specifically, the compilation engine performs logical blocking on the logical instructions of the quantum program, grouping the 1- and 2-qubit operations into groups of qubits (e.g., subsets of the entire set of qubits provided by the quantum processor). The size of these groupings may be determined based on a performance threshold of pulse optimization, limiting the group size such that the pulse optimization is able to be sufficiently optimized within a reasonable processing time. For example, it may be determined that the underlying pulse optimization algorithm performs adequately up to approximately ten qubits. As such, for a 50-qubit quantum processor, the compilation engine may break up logical instructions into five 10-qubit blocks, which achieves a reduced order of complexity for pulse optimization, allowing the pulse optimization to be performed on each block within a reasonable processing time." Examiner notes the above citation shows partitioning operations into smaller groups and segmenting them further or maintaining the group for scheduling purposes.);
converting each Gc member to a corresponding graph group (Ggc) (Para. [37], Chong shows "the compilation engine 114 performs logical blocking on logical assembly 316 generated from the previous operations. The logical assembly 316 can be abstracted as a gate dependence graph. FIG. 4A illustrates an example gate dependency graph, GDG 400. The example GDG 400 is constructed from a quantum circuit representing the quantum approximate optimization algorithm (“QAOA”) that solves the MAX_CUT problem for a triangle. The circuit is decomposed into a standard gate set. An identity instruction 410 is inserted as a virtual root for every GDG to connect instructions at depth 0. Because this virtual root is the identity instruction 410, it does not interfere with the computational result or latency. Further, each path is labelled by a corresponding qubit name. In the example shown here, the GDG 400 represents the quantum program after the module flattening of operation 312 (e.g., logical assembly 316, a “flattened” quantum program)." Examiner notes the above citation shows using the logical assembly groups compiled from the quantum program to create a graph.);
generating a respective group of solver results (Gsc), wherein each Gsc corresponds to a respective Gc member and to its corresponding contiguous code part comprising physical qubits (Para. [9], Chong shows 'The method also includes generating a logical schedule for the quantum program based on commutativity between the plurality of logical blocks. The method further includes generating a tentative physical schedule based on the logical schedule. The tentative physical schedule includes a mapping of the logical assembly instructions in the logical schedule onto a plurality of qubits of a quantum processor. The method also includes aggregating instructions together in the tentative physical schedule that do not reduce parallelism, thereby generating an updated physical schedule." Examiner notes the above citation shows the physical schedule mapping assembly instructions to physical qubits. The physical schedule can be considered a group of solver results as it connects the assembly instruction blocks (gc) with the physical qubits it has been mapped to.);
determining an amount of inter-operations (Asc) related to the contiguous code part corresponding to a respective Gsc (Para. [34], Chong shows "The optimal control unit module 242 optimizes control pulses for each aggregated instruction. More specifically, the optimal control unit module 242 numerically finds the optimal Hamiltonian path from a starting quantum state to a final quantum state. Consider a quantum system with a set of external control fields u.sub.1, . . . , u.sub.M that can be tuned in real time. Optimal control minimizes deviations from a target state by adjusting each control field u. In the example embodiment, the optimal control unit module 242 utilizes gradient ascent pulse engineering (“GRAPE”) algorithm." Examiner notes the above citation shows calculating the operations needed for each aggregated instruction which correlates to the grouped assembly instructions compiled from the quantum program.);
determining a group of inter-operation amounts (Gamnt) based on the Asc (Para. [29], Chong shows "the compilation engine provides a compilation framework that both segments the larger problem of scheduling operations on so many qubits into multiple smaller problems (e.g., groupings of qubits and subsets of the program instructions) as well as optimizes those groupings to foster parallelism and to address certain mismatches between the logical instructions of the compilation and the physical constraints of various types of quantum processors. More specifically, the compilation engine performs logical blocking on the logical instructions of the quantum program, grouping the 1- and 2-qubit operations into groups of qubits (e.g., subsets of the entire set of qubits provided by the quantum processor). The size of these groupings may be determined based on a performance threshold of pulse optimization, limiting the group size such that the pulse optimization is able to be sufficiently optimized within a reasonable processing time. For example, it may be determined that the underlying pulse optimization algorithm performs adequately up to approximately ten qubits. As such, for a 50-qubit quantum processor, the compilation engine may break up logical instructions into five 10-qubit blocks, which achieves a reduced order of complexity for pulse optimization, allowing the pulse optimization to be performed on each block within a reasonable processing time." Examiner notes the above citation shows determining the pulse amount related to grouping logical instructions);
and determining an optimal compiled code structure having a smallest amount of Gamnt members (Para. [29], Chong shows "the compilation engine provides a compilation framework that both segments the larger problem of scheduling operations on so many qubits into multiple smaller problems (e.g., groupings of qubits and subsets of the program instructions) as well as optimizes those groupings to foster parallelism and to address certain mismatches between the logical instructions of the compilation and the physical constraints of various types of quantum processors. More specifically, the compilation engine performs logical blocking on the logical instructions of the quantum program, grouping the 1- and 2-qubit operations into groups of qubits (e.g., subsets of the entire set of qubits provided by the quantum processor). The size of these groupings may be determined based on a performance threshold of pulse optimization, limiting the group size such that the pulse optimization is able to be sufficiently optimized within a reasonable processing time. For example, it may be determined that the underlying pulse optimization algorithm performs adequately up to approximately ten qubits. As such, for a 50-qubit quantum processor, the compilation engine may break up logical instructions into five 10-qubit blocks, which achieves a reduced order of complexity for pulse optimization, allowing the pulse optimization to be performed on each block within a reasonable processing time." Examiner notes the above citation shows determining an optimal schedule to run quantum programs by minimizing the total amount of pulses (operations).).
Chong does not disclose:
mapping logical qubits contained in each Gc member to different physical cores;
However, in the analogous art of Distribution of Quantum circuits, Andres-Martinez teaches:
mapping logical qubits contained in each Gc member to different physical cores (Pg.4, Andres-Martinez shows "our approach may distribute circuits across any number of QPUs, thus answering an open problem proposed by the previous authors.");
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andres-Martinez into the teachings of Chong to implement " mapping logical qubits contained in each Gc member to different physical cores”. The modification would have been obvious as one of ordinary skill in the art would be motivated scale up the number of qubits a quantum computing system can handle (Andres-Martinez ,Pg.1).
Regarding claim 3, Chong as modified teaches:
further comprising segmenting the code to two or more segments based on identifying code characteristics between adjacent segments (Para. [29], Chong shows "the compilation engine 114, in the example embodiment, takes the quantum program 112 as input, applying a series of transformations to produce control pulses (e.g., the optimized physical schedule 116) that implement the computation on the quantum computing device 130. Several operational objectives of the compilation engine 114, in the example embodiment, include: (A) breaking up the logical operations of the quantum program 112 into subsets, or blocks of qubits 134 (and their associated operations) such that an internal optimal control unit module (not shown in FIG. 1) is able to generate adequate optimization solutions for the subset of instructions; (B) addressing parallelism problems inherent in breaking up the logical operations into blocks; and (C) optimizing the logical operations based on the strengths and weaknesses of the underlying physical hardware." Examiner notes the above citation shows segmenting code further after compiling into logical instructions to further optimize. Examiner further notes addressing parallelism requires segmenting code segments while being aware of the logical instructions within to prevent issues.).
Regarding claim 4, Chong as modified teaches claim 1 as cited above, but does not disclose:
wherein each identified group has a minimum length difference in regards to inter-qubit logical operations.
However, in the analogous art of quantum circuit distribution, Andres-Martinez teaches:
wherein each identified group has a minimum length difference in regards to inter-qubit logical operations (Pg.11; Andres Martinez shows "1. obtain the hypergraph partitions of the current segment and the next one; 2. obtain their discrepancy score δ computed as in (3); 3. if the discrepancy δ is below the threshold ▲, view both segments as a single one (i.e. merge them) and return to step 1; otherwise obtain the distributed circuit of the current segment and continue the procedure until all segments have been distributed" Examiner notes the above citation shows a minimum length of difference, where the discrepancy can be considered the difference and the gate contain a number of qubits each representing inter-qubit operations).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andres-Martinez into the teachings of Chong to implement “wherein each identified group has a minimum length difference in regards to inter-qubit logical operations”. The modification would have been obvious as one of ordinary skill in the art would be motivated to optimize global interaction between qubits, to reduce communications across QPUs to a minimum (Andres-Martinez, Pg.3-4).
Regarding claim 5, Chong as modified teaches claim 1 as cited above, but does not disclose:
wherein at least part of the code segments are predetermined according to limiting qubit distribution in a segment by a ratio between a number of different qubits in a segment to a total number of inter-qubit operations not being greater than a predetermined threshold.
However, in the analogous art of quantum circuit distribution, Andres-Martinez teaches:
wherein at least part of the code segments are predetermined according to limiting qubit distribution in a segment by a ratio between a number of different qubits in a segment to a total number of inter-qubit operations not being greater than a predetermined threshold (Pg.11; Andres Martinez shows "1. obtain the hypergraph partitions of the current segment and the next one; 2. obtain their discrepancy score δ computed as in (3); 3. if the discrepancy δ is below the threshold ▲, view both segments as a single one (i.e. merge them) and return to step 1; otherwise obtain the distributed circuit of the current segment and continue the procedure until all segments have been distributed" Examiner notes the above citation shows segmenting quantum circuits and based on the qubits to gate (operations) allocated in both QPUs either combines and keeps the preliminary segments as is.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andres-Martinez into the teachings of Chong to implement “wherein at least part of the code segments are predetermined according to limiting qubit distribution in a segment by a ratio between a number of different qubits in a segment to a total number of inter-qubit operations not being greater than a predetermined threshold”. The modification would have been obvious as one of ordinary skill in the art would be motivated to optimize global interaction between qubits, to reduce communications across QPUs to a minimum (Andres-Martinez, Pg.3-4).
Regarding claim 6, Chong as modified teaches claim 1 as cited above, but does not disclose teaches:
further comprising identifying the second group based on a minimum length difference between chosen combinations.
However, in the analogous art of Quantum circuit distribution, Andres-Martinez teaches:
further comprising identifying the second group based on a minimum length difference between chosen combinations (Pg.11; Andres-Martinez shows "1. obtain the hypergraph partitions of the current segment and the next one; 2. obtain their discrepancy score δ computed as in (3); 3. if the discrepancy δ is below the threshold ▲, view both segments as a single one (i.e. merge them) and return to step 1; otherwise obtain the distributed circuit of the current segment and continue the procedure until all segments have been distributed" Examiner notes the above citation shows a minimum length of difference, where the discrepancy can be considered the difference and the gate contain a number of qubits each representing inter-qubit operations. Further shown is creating a group if the minimal discrepancy is not met.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andres-Martinez into the teachings of Chong to implement “further comprising identifying the second group based on a minimum length difference between chosen combinations”. The modification would have been obvious as one of ordinary skill in the art would be motivated to optimize global interaction between qubits, to reduce communications across QPUs to a minimum (Andres-Martinez, Pg.3-4).
Regarding claim 7, Chong as modified teaches claim 1 as cited above, but does not disclose teaches:
wherein converting Gc members to a respective graph group comprises: associating each logical qubit contained in the contiguous code part constituting a converted Gc member with a different vertex in the graph,
and associating each inter-qubit operation in the converted Gc member with a different edge between a pair of vertices corresponding to that operation.
However, in the analogous art of Quantum circuit distribution, Andres-Martinez teaches:
wherein converting Gc members to a respective graph group comprises: associating each logical qubit contained in the contiguous code part constituting a converted Gc member with a different vertex in the graph (Pg.5, Andres-Martinez shows "The algorithm in Figure 4 encodes all information about how the circuit's CZ gates may be grouped together (i.e. when they may share the same ebit, see Figure 2) by representing such groups as a single hyperedge. The algorithm runs in time linear O(n) in the number n of gates of the input circuit. Figure 5 shows an example execution. Each vertex in the hypergraph corresponds to either a wire or a CZ gate"),
and associating each inter-qubit operation in the converted Gc member with a different edge between a pair of vertices corresponding to that operation (Pg. 5, Andres-Martinez shows "To build the distributed circuit, add a cat-entangler and cat-disentangler for each cut, and then allocate all CZ gates to their corresponding QPU, connecting the relevant wires and ebit halves. This translation takes O(cuts + gates) steps. However, by construction of the hypergraph, we know that cuts 2 gates, and thus this transformation takes time O(n), i.e. linear in the number n of gates from the original circuit." Examiner notes that cuts are ebits. Which are shared between QPUs and used for inter-qubit operations).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andres-Martinez into the teachings of Chong to implement” wherein converting Gc members to a respective graph group comprises: associating each logical qubit contained in the contiguous code part constituting a converted Gc member with a different vertex in the graph, and associating each inter-qubit operation in the converted Gc member with a different edge between a pair of vertices corresponding to that operation“. The modification would have been obvious as one of ordinary skill in the art would be motivated to optimize global interaction between qubits, to reduce communications across QPUs to a minimum (Andres-Martinez, Pg.3-4).
Regarding claim 8, Chong as modified teaches claim 1 as cited above, but does not disclose teaches:
wherein mapping the logical qubits further comprises partitioning graph vertices into exclusive groups representing system cores such that groups number and magnitudes are constrained by a number of the system cores and a number of physical qubits within each core respectively while minimizing a total amount of resulting inter-group edges, which correspond to an amount of operations between different cores.
However, in the analogous art of Quantum circuit distribution, Andres-Martinez teaches:
wherein mapping the logical qubits further comprises partitioning graph vertices into exclusive groups representing system cores such that groups number and magnitudes are constrained by a number of the system cores and a number of physical qubits within each core respectively while minimizing a total amount of resulting inter-group edges, which correspond to an amount of operations between different cores (Pg.6; [Table 1], Andres-Martinez shows "Original number of qubits and CZ gates of each of the circuits. We distributed each of them across k different QPUs, with 4 ≤ k ≤ 16" Fig. 4; Pg.5, Andres Martinez shows "The algorithm in Figure 4 encodes all information about how the circuit’s CZ gates maybe grouped together (i.e. When they may share the same ebit, see Figure 2 ) by representing such groups as a single hyperedge. The algorithm runs in time linear O(n) in the number n of gates of the input circuit. Figure5 shows an example execution. Each vertex in the hypergraph corresponds to either a wire or a CZ gate; we will refer to them as wire-vertices and CZ-vertices respectively. The following theorem is the key insight that makes our approach successful. Theorem Given a circuit, each of its possible distributed implementations ( without altering the gate set or the gate order ) corresponds to a unique partition of its hypergraph (given by Figure 4) whose number of cuts equals the number of ebits required. The theorem implies that we may use third-party hypergraph partitioners to produce circuit distributions with low ebit count. We now explain the intuition behind the theorem. First, observe that any distribution is described by a hypergraph partition: assigning a wire vertex to a block indicates in which QPU the corresponding wire is allocated. Similarly, assigning a CZ-vertex to a block determines which QPU will perform the CZ operation. Accordingly, the CZ gate will be local or require communication (i.e. ebits) to access its target wires... use the well-known rules from Figure 6 to reorder CZ gates and some 1-qubit gates, pulling CZ gates as early in the circuit as possible. This brings CZ gates closer together, letting our algorithm implement larger groups of nonlocal CZ gates using a single ebit" Examiner notes the citation above shows creating a hypergraph with partioned quantum circuits, where in they further use the circuits reduced into hypergraphs to optimize ebit usage (operations done between cores)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andres-Martinez into the teachings of Chong to implement “wherein mapping the logical qubits further comprises partitioning graph vertices into exclusive groups representing system cores such that groups number and magnitudes are constrained by a number of the system cores and a number of physical qubits within each core respectively while minimizing a total amount of resulting inter-group edges, which correspond to an amount of operations between different cores”. The modification would have been obvious as one of ordinary skill in the art would be motivated to optimize global interaction between qubits, to reduce communications across QPUs to a minimum (Andres-Martinez, Pg.3-4).
Regarding claim [ 1 ], Chong as modified teaches claim 1 as cited above, but does not disclose teaches:
wherein determining the group of inter-operation amounts further comprises, when the Gnc member is an entire code segment, determining a corresponding group of inter-operation amounts (Gamnt) as the amount of inter-operations (Asc) associated with the Gnc member (Gse) corresponding to the entire code segment.
However, in the analogous art of Quantum circuit distribution, Andres-Martinez teaches:
wherein determining the group of inter-operation amounts further comprises, when the Gnc member is an entire code segment, determining a corresponding group of inter-operation amounts (Gamnt) as the amount of inter-operations (Asc) associated with the Gnc member (Gse) corresponding to the entire code segment (Pg.6; [Table 1], Andres-Martinez shows "Original number of qubits and CZ gates of each of the circuits. We distributed each of them across k different QPUs, with 4 ≤ k ≤ 16... the percentage of extra quantum memory required to store the ebit halves used for communication. The proportion is calculated by counting the maximum number of ebit halves stored simultaneously, and dividing it by the number of qubits in the original circuit. This overhead was considerably reduced from previous versions of our approach by limiting the number of gates allowed to be applied between two nonlocal CZ gates sharing an ebit, so that the corresponding ebit does not need to be stored over a long period of time." Examiner notes the table cited above shows amount of e-bit (inter-qubit operation used qubits) space overhead for an entire circuit (code). The ebit space overhead represents the qubits used for inter-qubit operations by the total qubits available for the quantum circuit (code segment)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andres-Martinez into the teachings of Chong to implement ”wherein determining the group of inter-operation amounts further comprises, when the Gnc member is an entire code segment, determining a corresponding group of inter-operation amounts (Gamnt) as the amount of inter-operations (Asc) associated with the Gnc member (Gse) corresponding to the entire code segment.”. The modification would have been obvious as one of ordinary skill in the art would be motivated to optimize global interaction between qubits, to reduce communications across QPUs to a minimum (Andres-Martinez, Pg.3-4).
Regarding claim 11, Chong as modified teaches claim 1 as cited above, but does not disclose teaches:
wherein determining the group of inter-operation amounts further comprises: for any Gnc member that is not an entire code segment, determining an associated Gamnt member by summing Asc amounts associated with all the Gsc members corresponding to the any Gnc member,
and based on a determination that there are code parts outside those Gsc members, for the code parts outside those Gsc members, the determined Gamnt further includes an amount of all Cse inter-operations belonging to the code parts outside those Gsc members.
However, in the analogous art of Quantum circuit distribution, Andres-Martinez teaches:
wherein determining the group of inter-operation amounts further comprises: for any Gnc member that is not an entire code segment, determining an associated Gamnt member by summing Asc amounts associated with all the Gsc members corresponding to the any Gnc member (Pg.5 [Table 1], Andres-Martinez shows "Reducing the problem to hypergraph partitioning lets us use third-party solvers such as KaHyPar [24]. We implemented this approach in the quantum circuit description language Quipper [39]; the code is available at [40]. Apart from extracting a hypergraph out of the input circuit (Figure 4), and building the distributed circuit from the resulting partition, we include some additional pre-processing and post-processing phases: Pre-processing 1 : transform the input circuit into an equivalent one using only one-qubit gates and CZ gates; Quipper provides specialised functionality to do so. Pre-processing 2 : use the well-known rules from Figure 6 to reorder CZ gates and some 1-qubit gates, pulling CZ gates as early in the circuit as possible. This brings CZ gates closer together, letting our algorithm implement larger groups of non-local CZ gates using a single ebit. As shown in Figure 6, doing so may create new 1-qubit gates, namely Pauli X gates. Using the same rules, these byproduct gates can be pushed to the end of the circuit, where they will cancel out with other byproduct gates, so the overhead is bounded by at most a single pair of extra Pauli (X and Z) gates per wire. Pre-processing 3 : in many circuits, the main group of qubits that another qubit interacts with varies between the different stages of the circuit. Then, if we were to use the hypergraph of the whole circuit, the different connectivities of each stage would be confounded, preventing the hypergraph partitioner from properly optimizing them. To account for this, we first run a procedure that detects significant changes in the circuit's qubit connectivity and splits the circuit into multiple segments accordingly. Each of these segments is then distributed using the approach presented in Section III A. Appendix B details this extra pre-processing procedure." Examiner notes the above citation shows partitioning a quantum program and making a hypergraph representation of the quantum circuit and segmenting it further (code segments) to find optimal groupings of gates where minimal cuts (ebits) are used. In doing this they determine the inter-operation amounts used by each partition and group to find the optimal quantum circuit distribution.),
and based on a determination that there are code parts outside those Gsc members, for the code parts outside those Gsc members, the determined Gamnt further includes an amount of all Cse inter-operations belonging to the code parts outside those Gsc members (Pg.5 [Table 1], Andres-Martinez shows "Reducing the problem to hypergraph partitioning lets us use third-party solvers such as KaHyPar [24]. We implemented this approach in the quantum circuit description language Quipper [39]; the code is available at [40]. Apart from extracting a hypergraph out of the input circuit (Figure 4), and building the distributed circuit from the resulting partition, we include some additional pre-processing and post-processing phases: Pre-processing 1 : transform the input circuit into an equivalent one using only one-qubit gates and CZ gates; Quipper provides specialised functionality to do so. Pre-processing 2 : use the well-known rules from Figure 6 to reorder CZ gates and some 1-qubit gates, pulling CZ gates as early in the circuit as possible. This brings CZ gates closer together, letting our algorithm implement larger groups of non-local CZ gates using a single ebit. As shown in Figure 6, doing so may create new 1-qubit gates, namely Pauli X gates. Using the same rules, these byproduct gates can be pushed to the end of the circuit, where they will cancel out with other byproduct gates, so the overhead is bounded by at most a single pair of extra Pauli (X and Z) gates per wire. Pre-processing 3 : in many circuits, the main group of qubits that another qubit interacts with varies between the different stages of the circuit. Then, if we were to use the hypergraph of the whole circuit, the different connectivities of each stage would be confounded, preventing the hypergraph partitioner from properly optimizing them. To account for this, we first run a procedure that detects significant changes in the circuit's qubit connectivity and splits the circuit into multiple segments accordingly. Each of these segments is then distributed using the approach presented in Section III A. Appendix B details this extra pre-processing procedure." Examiner notes the above citation shows partitioning a quantum program and making a hypergraph representation of the quantum circuit and segmenting it further (code segments) to find optimal groupings of gates where minimal cuts (ebits) are used. The segments are each optimized individually and distributed across QPUs showing an amount of inter-operations for each segment.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andres-Martinez into the teachings of Chong to implement “wherein determining the group of inter-operation amounts further comprises: for any Gnc member that is not an entire code segment, determining an associated Gamnt member by summing Asc amounts associated with all the Gsc members corresponding to the any Gnc member, and based on a determination that there are code parts outside those Gsc members, for the code parts outside those Gsc members, the determined Gamnt further includes an amount of all Cse inter-operations belonging to the code parts outside those Gsc members”. The modification would have been obvious as one of ordinary skill in the art would be motivated to optimize global interaction between qubits, to reduce communications across QPUs to a minimum (Andres-Martinez, Pg.3-4).
Regarding claim 12, Chong as modified teaches claim 11 as cited above, but does not disclose teaches:
wherein determining the group of inter-operation amounts further comprises, for any Gnc member that is not the entire code segment, determining the associated Gamnt member by applying a penalty for code transitions between Gsc members,
wherein the penalty associated with each transition is determined as the amount of inter-operations needed to transfer qubits between codes.
However, in the analogous art of Quantum circuit distribution, Andres-Martinez teaches:
wherein determining the group of inter-operation amounts further comprises, for any Gnc member that is not the entire code segment, determining the associated Gamnt member by applying a penalty for code transitions between Gsc members (Pg.5, Andres-Martinez shows "Reducing the problem to hypergraph partitioning lets us use third-party solvers such as KaHyPar [24]. We implemented this approach in the quantum circuit description language Quipper [39]; the code is available at [40]. Apart from extracting a hypergraph out of the input circuit (Figure 4), and building the distributed circuit from the resulting partition, we include some additional pre-processing and post-processing phases: Pre-processing 1 : transform the input circuit into an equivalent one using only one-qubit gates and CZ gates; Quipper provides specialised functionality to do so. Pre-processing 2 : use the well-known rules from Figure 6 to reorder CZ gates and some 1-qubit gates, pulling CZ gates as early in the circuit as possible. This brings CZ gates closer together, letting our algorithm implement larger groups of non-local CZ gates using a single ebit. As shown in Figure 6, doing so may create new 1-qubit gates, namely Pauli X gates. Using the same rules, these byproduct gates can be pushed to the end of the circuit, where they will cancel out with other byproduct gates, so the overhead is bounded by at most a single pair of extra Pauli (X and Z) gates per wire. Pre-processing 3 : in many circuits, the main group of qubits that another qubit interacts with varies between the different stages of the circuit. Then, if we were to use the hypergraph of the whole circuit, the different connectivities of each stage would be confounded, preventing the hypergraph partitioner from properly optimizing them. To account for this, we first run a procedure that detects significant changes in the circuit's qubit connectivity and splits the circuit into multiple segments accordingly. Each of these segments is then distributed using the approach presented in Section III A. Appendix B details this extra pre-processing procedure." Examiner notes the above citation shows partitioning a quantum program and making a hypergraph representation of the quantum circuit and segmenting it further (code segments) to find optimal groupings of gates where minimal cuts (ebits) are used. In doing this penalizing any grouping that does not reduce the ebit overhead.),
wherein the penalty associated with each transition is determined as the amount of inter-operations needed to transfer qubits between codes (Pg.3-4, Andres Martinez shows "In QCD, rather than optimising each
nonlocal operation separately, the focus is on the global interaction between qubits, as we need to group highly interacting qubits together, so that communication across QPUs is minimal." pg.6, [Table 1], Andres-Martinez shows in Table 1 that ebit space overhead is calculated by the proportion of ebits (used in inter-operations) to the total amount of qubits. Examiner notes the above citations show optimizing quantum programs by minimizing communitions between QPU's and by doing this it penalizes any possible quantum circuit distribution (QCD) that would require more inter-operations compared to another QCD).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andres-Martinez into the teachings of Chong to implement “wherein determining the group of inter-operation amounts further comprises, for any Gnc member that is not the entire code segment, determining the associated Gamnt member by applying a penalty for code transitions between Gsc members, wherein the penalty associated with each transition is determined as the amount of inter-operations needed to transfer qubits between codes”. The modification would have been obvious as one of ordinary skill in the art would be motivated to optimize global interaction between qubits, to reduce communications across QPUs to a minimum (Andres-Martinez, Pg.3-4).
Regarding claim 13, Chong as modified teaches claim 11 as cited above and teaches:
further comprising determining the optimal compiled code structure by: selecting a Gnc member which has a minimum Gsc member (Para. [9], Chong shows 'The method also includes generating a logical schedule for the quantum program based on commutativity between the plurality of logical blocks. The method further includes generating a tentative physical schedule based on the logical schedule. The tentative physical schedule includes a mapping of the logical assembly instructions in the logical schedule onto a plurality of qubits of a quantum processor. The method also includes aggregating instructions together in the tentative physical schedule that do not reduce parallelism, thereby generating an updated physical schedule." Par. [20], Chong shows "the compilation engine provides a compilation framework that both segments the larger problem of scheduling operations on so many qubits into multiple smaller problems (e.g., groupings of qubits and subsets of the program instructions) as well as optimizes those groupings to foster parallelism and to address certain mismatches between the logical instructions of the compilation and the physical constraints of various types of quantum processors. More specifically, the compilation engine performs logical blocking on the logical instructions of the quantum program, grouping the 1- and 2-qubit operations into groups of qubits (e.g., subsets of the entire set of qubits provided by the quantum processor). The size of these groupings may be determined based on a performance threshold of pulse optimization, limiting the group size such that the pulse optimization is able to be sufficiently optimized within a reasonable processing time. For example, it may be determined that the underlying pulse optimization algorithm performs adequately up to approximately ten qubits. As such, for a 50-qubit quantum processor, the compilation engine may break up logical instructions into five 10-qubit blocks, which achieves a reduced order of complexity for pulse optimization, allowing the pulse optimization to be performed on each block within a reasonable processing time." Examiner notes the above citation shows partitioning operations into smaller groups and segmenting them further or maintaining the group for scheduling purposes. Para. [29], Chong shows "the compilation engine 114, in the example embodiment, takes the quantum program 112 as input, applying a series of transformations to produce control pulses (e.g., the optimized physical schedule 116) that implement the computation on the quantum computing device 130. Several operational objectives of the compilation engine 114, in the example embodiment, include: (A) breaking up the logical operations of the quantum program 112 into subsets, or blocks of qubits 134 (and their associated operations) such that an internal optimal control unit module (not shown in FIG. 1) is able to generate adequate optimization solutions for the subset of instructions; (B) addressing parallelism problems inherent in breaking up the logical operations into blocks; and (C) optimizing the logical operations based on the strengths and weaknesses of the underlying physical hardware." Examiner notes the above citation shows optimizing a schedule (gsc) the quantum program is broken up into a plurality of groups and each group is optimized to their lowest qubit grouping possible.);
expressing the code in physical qubit terms according to the Gsc members corresponding to the selected Gnc member and the Cse code parts outside (Para. [20], Chong shows "the compilation engine provides a compilation framework that both segments the larger problem of scheduling operations on so many qubits into multiple smaller problems (e.g., groupings of qubits and subsets of the program instructions) as well as optimizes those groupings to foster parallelism and to address certain mismatches between the logical instructions of the compilation and the physical constraints of various types of quantum processors. More specifically, the compilation engine performs logical blocking on the logical instructions of the quantum program, grouping the 1- and 2-qubit operations into groups of qubits (e.g., subsets of the entire set of qubits provided by the quantum processor). The size of these groupings may be determined based on a performance threshold of pulse optimization, limiting the group size such that the pulse optimization is able to be sufficiently optimized within a reasonable processing time. For example, it may be determined that the underlying pulse optimization algorithm performs adequately up to approximately ten qubits. As such, for a 50-qubit quantum processor, the compilation engine may break up logical instructions into five 10-qubit blocks, which achieves a reduced order of complexity for pulse optimization, allowing the pulse optimization to be performed on each block within a reasonable processing time." Examiner notes the above citation shows the quantum program as a schedule and grouping them in terms of physical qubits. As the whole quantum program is scheduled all GNC and CSE code parts would also be expressed);
Chong as modified does not disclose teaches:
and adding inter-operations for transferring qubits between cores to the code.
However, in the analogous art of Quantum circuit distribution, Andres-Martinez teaches:
and adding inter-operations for transferring qubits between cores to the code (Pg.5, Andres-Martinez shows "To build the distributed circuit, add a cat-entangler and cat-disentangler for each cut, and then allocate all CZ gates to their corresponding QPU, connecting the relevant wires and ebit halves. This translation takes O(cuts + gates) steps. However, by construction of the hypergraph, we know that cuts 2 gates, and thus this transformation takes time O(n), i.e. linear in the number n of gates from the original circuit." Examiner notes the above citation shows adding the gates and e-bits needed for inter-operations between cores while building quantum circuits").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andres-Martinez into the teachings of Chong to implement ”adding inter-operations for transferring qubits between cores to the code”. The modification would have been obvious as one of ordinary skill in the art would be motivated to optimize global interaction between qubits, to reduce communications across QPUs to a minimum (Andres-Martinez, Pg.3-4).
Regarding claim 14, Chong as modified teaches claim 1 as cited above, but does not disclose teaches:
further comprising determining the amount of inter-operation amounts (Asc) is based on weighting that is associated with edges of a solver processed graphs.
However, in the analogous art of Quantum circuit distribution, Andres-Martinez teaches:
further comprising determining the amount of inter-operation amounts (Asc) is based on weighting that is associated with edges of a solver processed graphs (Pg.5, Andres Martinez shows "First, observe that any distribution is described by a hypergraph partition: assigning a wire-vertex to a block indicates in which QPU the corresponding wire is allocated. Similarly, assigning a CZ-vertex to a block determines which QPU will perform the CZ operation. Accordingly, the CZ gate will be local or require communication (i.e. ebits) to access its target wires. Notice that in Figure 5 each hyperedge connects a wire-vertex with multiple CZ-vertices: it represents all the locations where the wire's state is required. The number of cuts of a given hyperedge corresponds to the number of extra blocks it reaches (2), and for each of them an ebit is needed so the wire's state is accessible. Therefore, the number of cuts corresponds precisely to the number of ebits. Appendix A gives a detailed proof of the theorem. To build the distributed circuit, add a cat-entangler and cat-disentangler for each cut, and then allocate all CZ gates to their corresponding QPU, connecting the relevant wires and ebit halves. This translation takes O(cuts + gates) steps. However, by construction of the hypergraph, we know that cuts 2 gates, and thus this transformation takes time O(n), i.e. linear in the number n of gates from the original circuit." Pg.3-4, Andres Martinez shows "In QCD, rather than optimizing each nonlocal operation separately, the focus is on the global interaction between qubits, as we need to group highly interacting qubits together, so that communication across QPUs is minimal." Examiner notes the above citation shows optimizing and reducing the amount of inter-operations by grouping gates (edges) to optimize communication usage).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andres-Martinez into the teachings of Chong to implement “further comprising determining the amount of inter-operation amounts (Asc) is based on weighting that is associated with edges of a solver processed graphs”. The modification would have been obvious as one of ordinary skill in the art would be motivated to optimize global interaction between qubits, to reduce communications across QPUs to a minimum (Andres-Martinez, Pg.3-4).
Regarding claim 15, Chong as modified teaches claim 14 as cited above, but does not disclose teaches:
further comprising determining the Gamnt members by using weighted sums of inter-operations comprising at least associated qubit transfer operations.
However, in the analogous art of Quantum circuit distribution, Andres-Martinez teaches:
further comprising determining the Gamnt members by using weighted sums of inter-operations comprising at least associated qubit transfer operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Andres-Martinez into the teachings of Chong to implement “further comprising determining the Gamnt members by using weighted sums of inter-operations comprising at least associated qubit transfer operations”. The modification would have been obvious as one of ordinary skill in the art would be motivated to optimize global interaction between qubits, to reduce communications across QPUs to a minimum (Andres-Martinez, Pg.3-4).
With regards to claim 16, Chong as modified teaches the method of claim 1 and it is a claim having similar limitations as cited above in claim 1. Thus, claim 16 is also rejected under the same rationale as cited in the rejection of claim 1 above.
With regards to claim 17, Chong as modified teaches the non-transitory computer readable medium of claim 16 and it is a claim having similar limitations as cited in claim 3 above. Thus, claim 17 is also rejected under the same rationale as cited in the rejection of claim 3 above.
With regards to claim 18, Chong as modified teaches the non-transitory computer readable medium of claim 16 and it is a claim having similar limitations as cited in claim 4 above. Thus, claim 18 is also rejected under the same rationale as cited in the rejection of claim 4 above.
With regards to claim 19, Chong as modified teaches the non-transitory computer readable medium of claim 16 and it is a claim having similar limitations as cited in claim 5 above. Thus, claim 19 is also rejected under the same rationale as cited in the rejection of claim 5 above.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210334081 A1 (Hereinafter referred to as Chong) in view of ‘Automated Distribution of Quantum Circuits via Hypergraph Partitioning’ (Hereinafter referred to as Andres-Martinez) in further view of US 20080163183 A1 (Hereinafter referred to as Li).
Regarding claim 2, Chong as modified teaches claim 1 as cited above, but does not disclose:
further comprising remapping logical qubits to physical qubits such that cores having high latency physical connections are involved with fewer inter-operations per core relative to other cores.
However, in the analogous art of parameterized offloading on multiprocessor architectures, Li teaches:
further comprising remapping logical qubits to physical qubits such that cores having high latency physical connections are involved with fewer inter-operations per core relative to other cores (Para. [13], Li shows "A chip multiprocessor ("CMP") system, such as the system 500 illustrated in FIG. 5 and described below, provides for running multiple threads via concurrent thread execution on multiple cores (e.g., processor cores 502a-502n) on the same chip. In such CMP systems, one or more cores may be configured to, for example, coordinate main program flow, interact with an operating system, and execute tasks that are not offloaded (referred herein as a "main core" or "MC"); and one or more cores may be configured to execute tasks offloaded from the main core (referred herein as "helper core(s)" or "HCs"). In some example CMP systems (e.g., heterogeneous CMP systems), the main core runs at a relatively high frequency and the helper core(s) run at a relatively lower frequency. In some example CMP systems, the helper core(s) might also support instruction set extension specialized for data-level parallelism with vector instructions while the main core does not support the same extension. Thus, a program partitioned into tasks that are offloaded from a main core to helper core(s) may reduce execution times and reduce power consumption on the CMP system." Para. [16], Li shows "Tasks may also have multiple entry points such as, for example, a sequential loop, a function, a series of sequential loops and function calls, or any other instruction segment that may reduce scheduling and communication between multiple cores in a MP system. During execution, a task may be fused, aligned, and/or split for optimal use of local memory. That is, tasks need not be consecutive addresses of machine readable instructions in local memory. The remaining portion of the source code 102 that is not categorized into tasks may be represented as a unique task, referred to herein as a super-task." Examiner notes the above citation shows scheduling tasks/threads for multiple processors to reduce the latency created by data movement when operations happen between processors. It would be obvious to use a technique that is usable for classical computing and apply it to quantum computing. Where instead of scheduling threads or code blocks to code, quantum computing uses logical qubits and physical qubits apparent in quantum processors).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Li into the teachings of Chong as modified to implement ". The modification would have been obvious as one of ordinary skill in the art would be motivated reduce scheduling and communication between multiple cores in a MP system (Li, Para. [13]).
Claim(s) 9 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210334081 A1 (Hereinafter referred to as Chong) in view of ‘Automated Distribution of Quantum Circuits via Hypergraph Partitioning’ (Hereinafter referred to as Andres-Martinez) in further view of US 20240171889 A1(Hereinafter referred to as Litinsky).
Regarding claim 9, Chong as modified teaches claim 1 as cited above, but does not disclose:
wherein the inter-operations between different cores needed to transfer qubits comprise qubit teleportation.
However, in the analogous art of quantum computing, Litinsky teaches:
wherein the inter-operations between different cores needed to transfer qubits comprise qubit teleportation (Para. [326], Litinisky shows "As described below in some embodiments, quantum teleportation can be exploited to enable multiple logical gates that operate successively on the same logical qubit to be executed in parallel. The ability to execute gates in parallel can increase throughput of an active volume core of given size (N qubits), as will become apparent." Examiner notes the above citation shows qubits being teleported from one core to another to allow parallel execution).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Litinsky into the teachings of Chong as modified to implement “wherein the inter-operations between different cores needed to transfer qubits comprise qubit teleportation”. The modification would have been obvious as one of ordinary skill in the art would be motivated to allow multiple logic gates to execute on the same logical qubit in parallel.
With regards to claim 20, Chong as modified teaches the non-transitory computer readable medium of claim 16 and it is a claim having similar limitations as cited in claim 9 above. Thus, claim 20 is also rejected under the same rationale as cited in the rejection of claim 9 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20230020389 A1 – This prior art teaches scheduling on multiple QPUs
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/Z.A.M./Examiner, Art Unit 2193
/Chat C Do/Supervisory Patent Examiner, Art Unit 2193
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