DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kusunoki et al. (US 2024/0188330 A1 hereinafter referred to as “Kusunoki”).
With respect to claim 1, Kusunoki discloses, in Figs.1-57, a display apparatus comprising: a substrate (151); a first thin-film transistor (207G/M12) located on the substrate (151/102) and comprising a first semiconductor layer (208) and a first gate electrode (204) (see Par.[0587] wherein the display apparatus 50A illustrated in FIG. 36A includes transistors 205D, 205R, 205G, 207G, and 207B, light-emitting elements 130R, 130G, and 130B, and the like between the substrates 151 and 152; see Par.[0292]-[0293] wherein the transistor includes a conductive layer 204, a conductive layer 212a, a conductive layer 212b, the insulating layer 106, a semiconductor layer 208, an insulating layer 120, and a conductive layer 202; in the transistor 200, the conductive layer 204 serves as a gate electrode (also referred to as a first gate electrode), and part of the insulating layer 106 serves as a gate insulating layer (also referred to as a first gate insulating layer); see Par.[0282] wherein the conductive layer 112a is provided over the substrate 102 and the insulating layer 110 is provided over the conductive layer 112a); a second thin-film transistor (205G/M14) located on the substrate (151) and comprising a second semiconductor layer (108), a second gate electrode (104), a lower electrode (112a), and an upper electrode (112b) (see Par.[0281] wherein the transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b); and a lower conductive layer (112aA, 112aB) located between the substrate (102) and the first semiconductor layer (208), wherein a first angle between a channel region of the first semiconductor layer (208) and the substrate (102) is different from a second angle between a channel region of the second semiconductor layer (108) and the substrate (102), wherein the first gate electrode (204) and the second gate electrode (104) are located on a same layer (106), and the lower electrode (112aA, 112aB) and the lower conductive layer (112aA) are located on a same layer/(upper surface layer of substrate) (see Figs.33A-33B, wherein lower electrode 112aA, 112aB are located between substrate and semiconductor 208, 108; angle between semiconductor 108 and substrate is substantially 90o; angle between channel 208 and substrate is substantially 0o).
With respect to claim 2, Kusunoki discloses, in Figs.1-57, the display apparatus, wherein the first angle is 0° to 5°, and the second angle is 20° to 90°(see Figs.33A-33B, wherein lower electrode 112aA, 112aB are located between substrate and semiconductor 208, 108; angle between semiconductor 108 and substrate is substantially 90o; angle between channel 208 and substrate is substantially 0o).
With respect to claim 3, Kusunoki discloses, in Figs.1-57, the display apparatus, wherein the lower electrode (112aB) of the second thin-film transistor (M14) is connected to the lower conductive layer (112aB) (see Fig.31, wherein conductive 112aB intersect M12 and M14).
With respect to claim 4, Kusunoki discloses, in Figs.1-57, the display apparatus, wherein a central portion of the second semiconductor layer (108) is connected to the lower electrode (112aB), and a peripheral portion of the second semiconductor layer (108) is connected to the upper electrode (112bA) (see Figs.33A, 33B, 36A, 36B).
With respect to claim 5, Kusunoki discloses, in Figs.1-57, the display apparatus, further comprising a first insulating layer (110a) located between the lower electrode (112a) and the upper electrode (112b), wherein the first insulating layer (110a) comprises a first opening that extends to the lower electrode (112a), and at least a part of the second semiconductor layer (108) is located in the first opening (see Par.[0280] wherein the semiconductor device 10 includes a transistor 100, a transistor 200, a capacitor 150, and an insulating layer 110; see Par.[0320] wherein the insulating layer 110 illustrated in FIG. 20B and the like includes an insulating layer 110a, an insulating layer 110b over the insulating layer 110a, and an insulating layer 110c over the insulating layer 110b, for example).
With respect to claim 6, Kusunoki discloses, in Figs.1-57, the display apparatus, further comprising a second insulating layer (110c) covering the second semiconductor layer (108), wherein a thickness of the second insulating layer (110c) is less than a thickness of the first insulating layer (110a) (see Par.[0335]-[0338] wherein a thickness T110a of the insulating layer 110a can be greater than or equal to 3 nm, greater than or equal to 5 nm, greater than or equal to 10 nm, greater than or equal to 20 nm, greater than or equal to 50 nm, or greater than or equal to 70 nm and can be less than 1 m or less than or equal to 500 nm, less than or equal to 400 nm, less than or equal to 300 nm, less than or equal to 200 nm, less than or equal to 150 nm, or less than or equal to 120 nm; a thickness T110c of the insulating layer 110c can be greater than or equal to 3 nm, greater than or equal to 5 nm, greater than or equal to 10 nm, greater than or equal to 15 nm, or greater than or equal to 20 nm and can be less than or equal to 1 μm or less than or equal to 500 nm, less than or equal to 300 nm, less than or equal to 200 nm, less than or equal to 150 nm, or less than or equal to 120 nm, or less than or equal to 100 nm).
With respect to claim 7, Kusunoki discloses, in Figs.1-57, the display apparatus, further comprising a storage capacitor (C) comprising a first capacitor electrode (212a) and a second capacitor electrode (112b), wherein the first capacitor electrode is located on a same layer as the first gate electrode and the second gate electrode (see Par.[0541] wherein FIG. 29 illustrate a transistor M11 corresponding to the transistor M1, a transistor M12 corresponding to the transistor M2, a transistor M13 corresponding to the transistor M3, a transistor M14 corresponding to the transistor M4, a transistor M15 corresponding to the transistor M5, a transistor M16 corresponding to the transistor M6, a capacitor C11 corresponding to the capacitor C1, a capacitor C12 corresponding to the capacitor C2, a wiring GL1 corresponding to the wiring GLa, a wiring GL2 corresponding to the wiring GLb, a wiring GL3 corresponding to the wiring GLc, the wiring SL corresponding to the wiring DL, a wiring VL0 corresponding to the wiring 23, a wiring ANO corresponding to the wiring 21, and a pixel electrode 111 electrically connected to one electrode of the light-emitting element 32; see Par.[0570] wherein as illustrated in FIG. 33B, the capacitor C11 includes the conductive layers 112b and 212a and the insulating layer 106 interposed between the conductive layers 112b and 212a).
With respect to claim 8, Kusunoki discloses, in Figs.1-57, the display apparatus, wherein each of the first semiconductor layer (208) and the second semiconductor layer (108) comprises an oxide semiconductor (see Par.[0114], [0121]-[0122] wherein examples of the variety of semiconductors that can be used include compound semiconductors (e.g., silicon germanium and gallium arsenide) and oxide semiconductors in addition to semiconductors including mainly a single element (e.g., silicon and germanium); see Par.[0310]-[0315] wherein the semiconductor material used for the semiconductor layers 108 and 208; examples of the compound semiconductor include gallium arsenide and silicon germanium; other examples of the compound semiconductor include an organic semiconductor, a nitride semiconductor, and an oxide semiconductor; these semiconductor materials may contain an impurity as a dopant).
With respect to claim 9, Kusunoki discloses, in Figs.1-57, the display apparatus, further comprising a third thin-film transistor (207B) located on the substrate (151) and comprising a third semiconductor layer (208) and a third gate electrode (204), wherein each of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor, and the third semiconductor layer comprises a silicon semiconductor (see Par.[0587] wherein the display apparatus 50A illustrated in FIG. 36A includes transistors 205D, 205R, 205G, 207G, and 207B, light-emitting elements 130R, 130G, and 130B, and the like between the substrates 151 and 152; see Par.[0310]-[0315] wherein the semiconductor material used for the semiconductor layers 108 and 208; examples of the compound semiconductor include gallium arsenide and silicon germanium; other examples of the compound semiconductor include an organic semiconductor, a nitride semiconductor, and an oxide semiconductor; these semiconductor materials may contain an impurity as a dopant).
With respect to claim 10, Kusunoki discloses, in Figs.1-57, the display apparatus, wherein the third gate electrode is located above the third semiconductor layer (208) and below a first insulating layer (106), and the first semiconductor layer is located above the first insulating layer (see Fig.36A).
With respect to claim 11, Kusunoki discloses, in Figs.1-57, a display apparatus comprising: a substrate (151); a first insulating layer (110) located on the substrate (151) and comprising a first opening (143B) (see Par.[0280] wherein the semiconductor device 10 includes a transistor 100, a transistor 200, a capacitor 150, and an insulating layer 110; see Par.[0552] wherein an opening 143B of the transistor M14 is provided. In the conductive layer 112bB, an opening 143C of the transistor M15 is provided; in the conductive layer 112bC, an opening 143D of the transistor M16 is provided); a first thin-film transistor (M12) comprising a first semiconductor layer (208) and a first gate electrode (204), the first semiconductor layer (208) being located on a top surface of the first insulating layer (110); a second thin-film transistor (M14) comprising a second semiconductor layer (108) at least partially located in the first opening (143B), a lower electrode (112aB) located under the first insulating layer (110), an upper electrode (112bA) located over the first insulating layer (110), and a second gate electrode (104) located on the second semiconductor layer (108); and a second insulating layer (106) covering the first semiconductor layer (208) and the second semiconductor layer (108), wherein the first gate electrode (104) and the second gate electrode (204) are located on the second insulating layer (106) (see Par.[0587] wherein the display apparatus 50A illustrated in FIG. 36A includes transistors 205D, 205R, 205G, 207G, and 207B, light-emitting elements 130R, 130G, and 130B, and the like between the substrates 151 and 152; see Par.[0292]-[0293] wherein the transistor includes a conductive layer 204, a conductive layer 212a, a conductive layer 212b, the insulating layer 106, a semiconductor layer 208, an insulating layer 120, and a conductive layer 202; in the transistor 200, the conductive layer 204 serves as a gate electrode (also referred to as a first gate electrode), and part of the insulating layer 106 serves as a gate insulating layer (also referred to as a first gate insulating layer); see Par.[0282] wherein the conductive layer 112a is provided over the substrate 102 and the insulating layer 110 is provided over the conductive layer 112a; see Par.[0281] wherein the transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b).
With respect to claim 12, Kusunoki discloses, in Figs.1-57, the display apparatus, wherein an angle between an inner wall of the first opening and a top surface of the substrate is 20° to 90° (see Figs.33A-33B, wherein lower electrode 112aA, 112aB are located between substrate and semiconductor 208, 108; angle between semiconductor 108 and substrate is substantially 90o; angle between channel 208 and substrate is substantially 0o).
With respect to claim 13, Kusunoki discloses, in Figs.1-57, the display apparatus, further comprising a lower conductive layer (112aA, 112aB) located between the substrate (151/102) and the first semiconductor layer (208), wherein the lower electrode (112aB) is located on a same layer as the lower conductive layer (112aA, 112aB) (see Figs.33A, 33B).
With respect to claim 14, Kusunoki discloses, in Figs.1-57, the display apparatus, wherein a central portion of the second semiconductor layer (108) is connected to the lower electrode (112aB), and a peripheral portion of the second semiconductor layer (108) is connected to the upper electrode (112bA) (see Figs.33A, 33B).
With respect to claim 15, Kusunoki discloses, in Figs.1-57, the display apparatus, wherein a thickness of the second insulating layer is less than a thickness of the first insulating layer (see Par.[0335]-[0338] wherein a thickness T110a of the insulating layer 110a can be greater than or equal to 3 nm, greater than or equal to 5 nm, greater than or equal to 10 nm, greater than or equal to 20 nm, greater than or equal to 50 nm, or greater than or equal to 70 nm and can be less than 1 m or less than or equal to 500 nm, less than or equal to 400 nm, less than or equal to 300 nm, less than or equal to 200 nm, less than or equal to 150 nm, or less than or equal to 120 nm; a thickness T110c of the insulating layer 110c can be greater than or equal to 3 nm, greater than or equal to 5 nm, greater than or equal to 10 nm, greater than or equal to 15 nm, or greater than or equal to 20 nm and can be less than or equal to 1 μm or less than or equal to 500 nm, less than or equal to 300 nm, less than or equal to 200 nm, less than or equal to 150 nm, or less than or equal to 120 nm, or less than or equal to 100 nm).
With respect to claim 16, Kusunoki discloses, in Figs.1-57, the display apparatus, wherein each of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor (see Par.[0114], [0121]-[0122] wherein examples of the variety of semiconductors that can be used include compound semiconductors (e.g., silicon germanium and gallium arsenide) and oxide semiconductors in addition to semiconductors including mainly a single element (e.g., silicon and germanium); see Par.[0310]-[0315] wherein the semiconductor material used for the semiconductor layers 108 and 208; examples of the compound semiconductor include gallium arsenide and silicon germanium; other examples of the compound semiconductor include an organic semiconductor, a nitride semiconductor, and an oxide semiconductor; these semiconductor materials may contain an impurity as a dopant).
With respect to claim 17, Kusunoki discloses, in Figs.1-57, the display apparatus, further comprising a storage capacitor (C) comprising a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is located on a same layer as the first gate electrode and the second gate electrode (see Par.[0541] wherein FIG. 29 illustrate a transistor M11 corresponding to the transistor M1, a transistor M12 corresponding to the transistor M2, a transistor M13 corresponding to the transistor M3, a transistor M14 corresponding to the transistor M4, a transistor M15 corresponding to the transistor M5, a transistor M16 corresponding to the transistor M6, a capacitor C11 corresponding to the capacitor C1, a capacitor C12 corresponding to the capacitor C2, a wiring GL1 corresponding to the wiring GLa, a wiring GL2 corresponding to the wiring GLb, a wiring GL3 corresponding to the wiring GLc, the wiring SL corresponding to the wiring DL, a wiring VL0 corresponding to the wiring 23, a wiring ANO corresponding to the wiring 21, and a pixel electrode 111 electrically connected to one electrode of the light-emitting element 32; see Par.[0570] wherein as illustrated in FIG. 33B, the capacitor C11 includes the conductive layers 112b and 212a and the insulating layer 106 interposed between the conductive layers 112b and 212a).
With respect to claim 18, Kusunoki discloses, in Figs.1-57, the display apparatus, further comprising a third thin-film transistor (207B) located on the substrate and comprising a third semiconductor layer and a third gate electrode, wherein each of the first semiconductor layer and the second semiconductor layer comprises an oxide semiconductor, and the third semiconductor layer comprises a silicon semiconductor (see Par.[0587] wherein the display apparatus 50A illustrated in FIG. 36A includes transistors 205D, 205R, 205G, 207G, and 207B, light-emitting elements 130R, 130G, and 130B, and the like between the substrates 151 and 152; see Par.[0292]-[0293] wherein the transistor includes a conductive layer 204, a conductive layer 212a, a conductive layer 212b, the insulating layer 106, a semiconductor layer 208, an insulating layer 120, and a conductive layer 202; in the transistor 200, the conductive layer 204 serves as a gate electrode (also referred to as a first gate electrode), and part of the insulating layer 106 serves as a gate insulating layer (also referred to as a first gate insulating layer); see Par.[0282] wherein the conductive layer 112a is provided over the substrate 102 and the insulating layer 110 is provided over the conductive layer 112a; see Par.[0281] wherein the transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b).
With respect to claim 19, Kusunoki discloses, in Figs.1-57, the display apparatus, wherein the third gate electrode is located above the third semiconductor layer and below a first insulating layer, and the first semiconductor layer is located above the first insulating layer (see Figs.33A, 33B).
With respect to claim 20, Kusunoki discloses, in Figs.1-57, the display apparatus, wherein the substrate comprises a display area and a peripheral area around the display area, wherein the display apparatus further comprises a built-in driving thin-film transistor located in the peripheral area, wherein the built-in driving thin-film transistor is a vertical-type thin-film transistor (see Par.[0103]-[0104], [0125], [0129] wherein the transistor M2 has a function of controlling the emission intensity of the light-emitting element 32; in this specification and the like, a transistor that functions like the transistor M2 is sometimes referred to as “driving transistor”).
Citation of Pertinent Prior Art
The prior art made of record (e.g., see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
