Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Priority document with application number 2023-139535 has been filed as of 5 February 2026.
Specification
The title of the invention has been amended to overcome the objection to the specification.
A substitute specification has been filed to overcome the objections to the specification. The objections to the specification are withdrawn.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
The claims have been amended to overcome the objections to the claims. The objections to the claims are withdrawn.
The claims have been amended to overcome the indefiniteness issues.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4, and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP 2013125562 (Okuno, et al., hereinafter Okuno).
Regarding claim 1, Okuno teaches a memory device (Okuno, “semiconductor memory device” (FIG. 1)) comprising: a control circuit (Okuno, [0008]: “a first control circuit for controlling an activity and a non-activity of the word line in response to an active command and a write command”) configured to receive an initialization mode signal transmitted from an initialization control circuit (Okuno, “control circuit unit 18”) (Okuno, [0075]: “Therefore, in the present embodiment, the above-described refresh operation executed in response to the active command signal ACT is referred to as "initialization"”) and to generate an internal clock (Okuno, [0026]: “internal clock signal CLK”) and a write control signal; (Okuno, [0028]: “write command signal”) an I/O input circuit configured to apply a low level to a true side or a bar side of each bit line of a plurality of bit lines (Okuno, [0038]: “input/output circuit 20”) according to initialization data transmitted from the initialization control circuit; (Okuno, [0038]: “ That is, in the read operation, the data latch circuit 19 latches the read data supplied from the data control circuit unit 18 and supplies the read data to the input/output circuit 20 in synchronization with the data strobe signal DQS. In the write operation, the data latch circuit 19 latches the data supplied from the input/output circuit 20 on the basis of the data strobe signal DQS, and supplies the data to the data control unit 18 as write data. The input/output buffer unit 20 is a circuit that functions as an interface for mutually converting an internal signal and an external signal of the semiconductor memory device 10.”) and a selection circuit configured to select a plurality of word lines and the plurality of bit lines at a same time as one another, (Okuno, [0036]: “The memory cell array 171 includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC provided at respective intersections of the plurality of word lines WL and the plurality of bit lines BL. A plurality of memory cells MC belonging to the same row are commonly connected to each word line WL…”) and to simultaneously write the initialization data in a bulk into a plurality of memory cells connected to the selected plurality of word lines and selected plurality of bit lines. (Okuno, [0021]: “According to the series of operations described above, the data "H" is applied to the bit lines BL 1 to BL 3 respectively connected to the memory cells MC 1 to MC 3 at a time earlier than the bit line BL 4 to which the memory cell MC 4 is connected. However, in this stage, since the word line WL is in the lowered state, the data "H" applied to the bit lines BL 1 to BL 3 is not written to the memory cells MC 1 to MC 3. When the word line WL is raised at time t 7, data is simultaneously written to the memory cells MC 1 to MC 4.”)
Regarding claim 4, Okuno teaches the memory device according to claim 1, wherein a word driver section connected to the selection circuit lowers a high level potential of the selected plurality of word lines. (Okuno, [0087]: “The word line WL is driven to a high level for a period of the pulse width of the one-shot pulse signal. In this manner, when the word line WL is driven to the high level by the one-shot pulse signal, the data BLT 0 to Y [3: 0], BLT 1 to Y [3: 0] of the plurality of bits appear on a plurality of bit lines connected to the memory cells CELL 0 to Y 0 to CELL 0 to Y 3, and CELL 1 to Y 0 to CELL 1 to Y 3. Therefore, when the word line WL is driven to the high level by the one-shot pulse signal, the data signals BLT 0 to Y [3: 0], BLT 1 to Y [3: 0] on the bit line are simultaneously written to the plurality of memory cells CELL 0 to Y 0 to CELL 0 to Y 3, and CELL 1 to Y 0 to CELL 1 to Y 3.”)
Regarding claim 6, Okuno teaches the memory device according to claim 1, and teaches wherein the memory device is an SRAM macro. (Okuno, [0012]: “control logic unit included in the semiconductor memory device”; [0024]: “In FIG. 2A, the semiconductor memory device 10 includes a clock generator unit 11, a command decoder unit 12, a mode register unit 13, a control logic unit 14, a row address buffer unit 15, a column address buffer unit 16, a memory unit 17, a data control unit 18, a data latch circuit unit 19, and an input/output buffer unit 20.”)
Allowable Subject Matter
Claims 2-3 and 5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not appear to teach the subject matter of claim 2, including a memory device comprising: a control circuit configured to receive an initialization mode signal transmitted from an initialization control circuit and to generate an internal clock and a write control signal; an I/O input circuit configured to apply a low level to a true side or a bar side of each bit line of a plurality of bit lines according to initialization data transmitted from the initialization control circuit; and a selection circuit configured to select a plurality of word lines and the plurality of bit lines at a same time as one another, and to simultaneously write the initialization data in a bulk into a plurality of memory cells connected to the selected plurality of word lines and selected plurality of bit lines, wherein the initialization control circuit generates an initialization address area mask signal that masks an area to be initialized, and the selection circuit masks an initialization of a part of an address area based on the initialization address area mask signal.
The prior art of record does not appear to teach the subject matter of claim 3, including a memory device comprising: a control circuit configured to receive an initialization mode signal transmitted from an initialization control circuit and to generate an internal clock and a write control signal; an I/O input circuit configured to apply a low level to a true side or a bar side of each bit line of a plurality of bit lines according to initialization data transmitted from the initialization control circuit; and a selection circuit configured to select a plurality of word lines and the plurality of bit lines at a same time as one another, and to simultaneously write the initialization data in a bulk into a plurality of memory cells connected to the selected plurality of word lines and selected plurality of bit lines, wherein the initialization control circuit generates an initialization data mask signal that masks data to be initialized, and the I/O input circuit masks a part of an I/O input of each memory cell of the plurality of memory cells according to the initialization data mask signal.
The prior art of record does not appear to teach the subject matter of claim 5, including a memory device comprising: a control circuit configured to receive an initialization mode signal transmitted from an initialization control circuit and to generate an internal clock and a write control signal; an I/O input circuit configured to apply a low level to a true side or a bar side of each bit line of a plurality of bit lines according to initialization data transmitted from the initialization control circuit; and a selection circuit configured to select a plurality of word lines and the plurality of bit lines at a same time as one another, and to simultaneously write the initialization data in a bulk into a plurality of memory cells connected to the selected plurality of word lines and selected plurality of bit lines, wherein the memory device is communicatively coupled to an error detection/correction circuit that is disposed between the initialization control circuit and the memory device, the memory device receives, from the error detection/correction circuit, the initialization mode signal, the initialization data, an initialization data mask signal that masks data to be initialized, an initialization address area mask signal that masks an area to be initialized, and an error detection/correction code, and initializes data of the plurality of memory cells in bulk.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL JOHN KING/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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