DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species B, claims 1-10 in the reply filed on 03 April 2026 is acknowledged. The traversal is on the ground(s) that “In particular, it is respectfully submitted that it should be no serious burden on the Examiner to consider both species in the single application.” This is not found persuasive because although there is no requirement to show separate classification in regards to an election of species, a burden does exist because a separate search would be required.
The requirement is still deemed proper and is therefore made FINAL.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The references cited in the information disclosure statement (IDS) submitted on 05 May 2025, have been considered.
Drawings
The drawings received on 16 August 2024 are accepted.
Specification
1. The disclosure is objected to because of the following informalities: at page 1, paragraph 0001, U.S. Patent Application No. 17/820,967 is now United States Patent No. 12,090,757.
2. The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ng et al. (US 2021/0354444).
With respect to claim 1, Ng discloses an operation method of a heater device (Fig. 2, element 204) with a memory unit (Fig. 2, element 210), wherein the heater device has a burning mode (paragraph 0025), a reading mode (paragraphs 0026-0027) and a heating mode (paragraph 0042), the heater device comprises a plurality of heater circuits (Fig. 2, element 206), each of the plurality of heater circuits comprises a first transistor (Fig. 3, element 308) and a second transistor (Fig. 3, element 306), a memory unit (Fig. 3, element 304) and a heater (Fig. 3, element 302) are respectively electrically connected (Fig. 3, Fire Line, N1) to the first transistor and the second transistor, and the method comprises:
in the burning mode (paragraph 0025 and paragraph 0043, i.e. element 304 is part of element 210), selectively turning on at least one of the first transistors (Fig. 3, element 308) according to a first signal (Fig. 2, element 214; paragraph 0045, i.e. ID), so that a first current generated by voltage signals (Fig. 3, Fire Line) coupled to two terminals of the first transistor passes through the memory unit (paragraphs 0025, 0045, i.e. during programming);
in the reading mode (paragraphs 0026-0027), sequentially turning on the first transistors (Fig. 3, element 308; paragraph 0045) to determine states of the memory units (Fig. 3, element 304); and
in the heating mode (paragraph 0042), selectively turning on at least one of the second transistors (Fig. 3, element 306) according to a second signal (Fig. 2, element 214; paragraph 0045, i.e. inverse ID), so that a second current generated by voltage signals (Fig. 3, Fire Line) coupled to two terminals of the second transistor passes through the heater (Fig. 3, element 302).
The examiner notes to applicant that the limitations concerning the burning mode, reading mode, and heating mode are broad in scope and would have been obvious to one of ordinary skill in the art in view of Ng as applied above.
With respect to claim 2, Ng discloses in the burning mode (paragraph 0025), the voltage signals (Fig. 3, Fire Line) coupled to the two terminals of the second transistors (Fig. 3, element 306) are disconnected (paragraph 0045, i.e. 306 OFF).
With respect to claim 3, Ng discloses in the reading mode (paragraphs 0026-0027), the voltage signals (Fig. 3, Fire Line) coupled to the two terminals of the second transistors (Fig. 3, element 306) are disconnected (paragraph 0045, i.e. 306 OFF).
With respect to claim 4, Ng discloses in the heating mode (paragraph 0042), the voltage signals (Fig. 3, Fire Line) coupled to the two terminals of the first transistors (Fig. 3, element 308) are disconnected (paragraph 0045, i.e. 308 OFF).
With respect to claim 5, Ng discloses a first terminal of the first transistor (Fig. 3, element 308) and a first terminal of the second transistor (Fig. 3, element 306) are electrically connected to each other (Fig. 3, Fire Line, N1).
With respect to claim 6, Ng discloses the first terminal of the first transistor (Fig. 3, element 308) is a gate terminal (paragraphs 0044-0046), and the first terminal of the second transistor (Fig. 3, element 308) is a gate terminal (paragraphs 0044-0046).
With respect to claim 7, Ng discloses the memory unit (Fig. 3, element 304) according to claim 5, wherein the memory unit (Fig. 3, element 304) is electrically connected to a second terminal of the first transistor (Fig. 3, element 308), and the heater (Fig. 3, element 302) is electrically connected to a second terminal of the second transistor (Fig. 3, element 306).
With respect to claim 8, Ng discloses the first transistor (Fig. 3, element 308) and the second transistor (Fig. 3, element 308) are transistors with the same doping type.
The examiner notes to applicant that although Ng does not disclose the doping type of the first transistor and the doping type of the second transistor, providing the first and second transistors with the same doping type simplifies manufacturing allowing the transistors to be formed in the same step by the same process and thus would have been obvious to one of ordinary skill in the art at the time of the invention.
Allowable Subject Matter
1. Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The primary reasons for allowance for claim 9 is that applicant’s claimed invention includes an operation method of a heater device with a memory unit, the heater device having a first transistor and a second transistor, wherein the first transistor and the second transistor are transistors with different doping types. It is this limitation, expressed in the claimed combination not found, taught, or suggested in the prior art that makes this claim allowable over the prior art.
2. Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The primary reasons for allowance for claim 10 is that applicant’s claimed invention includes an operation method of a heater device with a memory unit, the heater device having a first transistor and a second transistor, wherein the first transistor is an N-type transistor, and a second terminal of the first transistor electrically connected to the memory unit is a drain terminal. It is this limitation, expressed in the claimed combination not found, taught, or suggested in the prior art that makes this claim allowable over the prior art.
Conclusion
In view of the foregoing, the above claims have failed to patentably distinguish over the applied art.
The remaining references listed on forms 892 and 1449 have been reviewed by the examiner and are considered to be cumulative to or less material than the prior art references relied upon in the rejection above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Geoffrey Mruk whose telephone number is (571)272-2810. The examiner can normally be reached M-F 8-4:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ricardo Magallanes can be reached at (571) 272-5960. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GEOFFREY S MRUK/Primary Examiner, Art Unit 2853 05/11/2026
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