Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over MISAKI; US 20200127012 A1.
Regarding claims 1, Misaki teaches an electronic device (see figs. 28, 7, 1-58), comprising: a substrate (i.e., 1, or 51..); and a plurality of “units” disposed on the substrate (shown in fig. 28, 7), wherein a portion of the plurality of units comprises:
a conductive layer 7pe having a first opening (ch) penetrating through the conductive layer 7pe or 55 (shown in at least fig. 28/31 or see fig. 7); and
an insulating layer (i.e., 4, 11) disposed on the conductive layer 7pe and comprising
a second opening penetrating through the insulating layer (shown in at least fig. 28A/31).
wherein the first opening of the conductive layer and the second opening of the insulating layer are at least partially overlapped (shown in at least fig. 28A), wherein a width of the first opening of the conductive layer is greater than a width of the second opening of the insulating layer (shown in at least fig. 28A).
However, Masaki does not explicitly state the above first or second “opening” . Nonetheless, it is obvious to a person of ordinary skill in the art when the invention was made that the discontinuity or slot creating a gap/apace is/known as opening for reduction of the parasitic capacitance and efficient signal transmission.
The statements advanced in rejection of claim 1, above, as to the applicability and disclosure of Masaki and the motivation are incorporated herein in rejection of the following claims as follows:
2. The electronic device as claimed in claim 1, wherein the conductive layer comprises a metal material (see parag. 0119).
3. The electronic device as claimed in claim 1, wherein the insulating layer comprises an inorganic material (at least parag. 0174).
4. The electronic device as claimed in claim 1, wherein the insulating layer has a multi-layered structure (see fig. 28A, items 4,11).
5. The electronic device as claimed in claim 4, wherein the insulating layer comprises a first inorganic layer and a second inorganic layer, wherein the first inorganic layer and the second inorganic layer are of different materials (see at least parag. 0174, 0179).
6. The electronic device as claimed in claim 5, wherein the first inorganic layer is a silicon oxide layer, and the second inorganic layer is a silicon nitride layer (see at least parag. 0167).
7. The electronic device as claimed in claim 1, wherein the electronic device is an antenna device (parag.0109).
8. The electronic device as claimed in claim 1, wherein the electronic device is a display device (parag. 0123).
9. The electronic device as claimed in claim 1, wherein the electronic device is a light-emitting device (see at least parag. 0109).
Citation of Relevant Prior Art
Prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. In accordance with MPEP 707.05 the following references are pertinent in rejection of this application since they provide substantially the same information disclosure as this patent does. These references are:
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Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAVEH C KIANNI whose telephone number is (571)272-2417. The examiner can normally be reached on 9-19.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hollweg can be reached on 570-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KAVEH C KIANNI/Primary Examiner, Art Unit 2874
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