The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
This office action has been issued in response to the response filed 5/19/26. Claims 1-19 are pending in this application. Applicant's arguments have been carefully considered, but are not persuasive in view of the “response to arguments” section below. The examiner appreciates Applicant's effort to distinguish over the cited prior art by presenting arguments/amendments in an attempt to distinguish or clarify the claimed invention, however, upon further consideration and/or search, the claims remain unpatentable over the cited prior art for the reasons articulated in the “response to arguments” section below. All claims pending in the instant application remain rejected and clarification and/or elaboration regarding why the claims are not in condition for allowance will hereafter be provided in order to efficiently further prosecution. Accordingly, this action is made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-8, 10, 12-14, 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Bassett (US PGPUB # 20100228944) in view of Ramaraju (US PGPUB # 20130046927) further in view of Randall et al (US PGPUB # 20220308999).
With respect to independent claims 1, 18, 19 Bassett/Ramaraju discloses: An apparatus [Bassett abstract], comprising:
first control information storage and second control information storage separate from the first control information storage [TLB stores page entries and variable page size memory stores page size information, both are separate/distinct “stores/storages” used together for translating addresses - Bassett fig 1; Bassett does not explicitly disclose a second/separate imprecise storage. Nevertheless in the same field of endeavor, Ramaraju teaches means for speculative lookup where an imprecise/speculative storage (TAG array) stores a plurality of control information entries each control information entry corresponding to a given address and providing control information for controlling processing operations relating to the given address – Ramaraju abstract, fig 1, 3-4, paragraph 0020] [L1 MMU tag circuit and separate operand adder circuit and pg/pgz logic work together so that TAG arrays store tag and permission bits while speculative indexed CAM arrays are another control storage used in parallel for translation – Ramaraju 0020-0024 ] [snoop filter storage circuitry stores snoop filter entries with sharer information, the entry can be encoded two ways, precise/imprecise implemented as distinct fields/arrays – Randall abstract, fig 4-5],
wherein the first control information storage and the second control information storage are configured to store a plurality of control information entries, each control information entry corresponding to a given address and providing control information for controlling processing operations relating to the given address [TLB 112/205/305 stores multiple entries; Each of the entries 220-223 includes a payload comprising a physical page number (PPN), a mask, a cacheability bit (C), a read bit (R), a write bit (W), and a permission bit (P). Although three representative virtual side entries 210-214 and three representative physical side entries 220-223 are depicted in the system 200, it will be understood that the TLB 205 may include any number of entries/page sizes – Bassett 0023, fig 2-3. Bassett does not explicitly disclose a second, imprecise storage. Nevertheless in the same field of endeavor, Ramaraju teaches means for speculative lookup where an imprecise/speculative storage (TAG array) stores a plurality of control information entries each control information entry corresponding to a given address and providing control information for controlling processing operations relating to the given address – Ramaraju abstract, fig 1, 3-4, paragraph 0020] [];
lookup circuitry [TLB functions as lookup circuitry – Bassett fig 1] configured to:
perform a precise lookup operation in the first control information storage to identify a target control information entry corresponding to a target address determined based on a plurality of target address calculation operands [multiple operands (base address and offset) are used to perform a precise lookup by TLB using an effective address to identify a target entry corresponding to target address – Bassett fig 1-3, paragraph 0020-0022], and
perform, in parallel with the precise lookup operation [method 500 of translating virtual addresses to physical addresses in a base plus offset addressing mode wherein a first TLB lookup based on a base address is performed while adding the base + offset value concurrently such that the imprecise/base-only lookup is functionally performed in parallel with the precise/base+offset, such that base-only/imprecise TLB lookup is treated as speculative/imprecise relative to final effective address - Bassett 0040-0046] [parallel computation of effective address EA with computation of TAG and data access – Ramaraju 0009, fig 2] [snoop filter entry has both precise+imprecise encoding for sharer information and sharer count values, when snoop filter is accessed for target address the lookup logic observes both sets of fields in one access, in parallel, and the imprecise encoding describes which sharers hold cached data at granularity less precise than granularity of sharer with sharer count values indicating the # of sharers – Randall fig 4-5] an imprecise lookup operation in the second control information storage to identify the target control information entry based on an imprecise lookup value determined based on at least one of the target address calculation operands [performing first/speculative lookup using base address only to retrieve a speculative physical address – Bassett 0004-0007, fig 4]; and
checking circuitry configured to cause a miss to be detected in the second control information storage in response to determining that the imprecise lookup value does not correspond to the target address determined based on the plurality of target address calculation operands [The comparison circuit is configured to compare the base address value and the effective address value to determine whether a speculative translation of the base address value is valid by determining whether a page boundary has been crossed. The page boundary signal is output from the comparison circuit and received by the selection circuit. If a page boundary has been crossed, then the speculative physical address resulting from the first lookup operation is not correct or is not valid – Bassett 0020] [hit/miss signal/information – Ramaraju fig 1, abstract].
Bassett does not explicitly disclose a second control information storage for facilitating an imprecise lookup, although Bassett at least suggests this by teaching the imprecise lookup functionality using only a base address and the base address would need to be stored in a storage, as discussed with reference to fig 4 of Bassett above. Nevertheless in the same field of endeavor, Ramaraju teaches a plurality of speculative tag/TLB arrays (Ramaraju abstract, fig 1, paragraph 0022) operable to store control data for facilitating an imprecise/speculative lookup.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to implement a second control information storage for facilitating an imprecise lookup in the invention of Bassett as taught by Ramaraju because it would be advantageous for improving memory access by making lookup operations faster and/or more efficient (Ramaraju 0005-0006, 0024).
Bassett/Ramaraju does not explicitly disclose two distinct per-address control information storages/encodings (precise/imprecise) used for lookup. Nevertheless in the same field of endeavor Randall teaches two distinct per-address control information storages/encodings (precise/imprecise) used for lookup (Randall abstract, fig 2a/b, 4-6)
Therefore, Bassett/Ramaraju/Randall teaches all limitations of the instant claim(s).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to implement two distinct per-address control information storages/encodings (precise/imprecise) used for lookup in the invention of Bassett/Ramaraju as taught by Randall because it would be advantageous for improving utilisation of storage in a snoop filter and reduce the overhead in determining whether a given snoop filter entry has become stale (Randall 0038).
With respect to dependent claim 3 Bassett/Ramaraju/Randall discloses wherein the lookup circuitry is responsive to a determination that the imprecise lookup value used for a given imprecise lookup operation does not correspond to the target address, to allow forward progress based on the miss in the second control information storage without attempting to repeat the given imprecise lookup operation using a lookup value corresponding to the target address [forward progress ensured to the extent that if speculative/imprecise lookup is not correct, a precise lookup is performed to ensure forward progress – Bassett 0045-0046]
With respect to dependent claim 4 Bassett/Ramaraju/Randall discloses wherein the lookup circuitry is configured to initiate the imprecise lookup operation for a given target control information entry based on at least one of the target address calculation operands before the target address is made available [Bassett fig 4 step 404].
With respect to dependent claim 5 Bassett/Ramaraju/Randall discloses address calculation circuitry to determine the target address based on a combination of a base address and an offset, wherein the lookup circuitry is configured to exclude the offset from calculation of the imprecise lookup value [Bassett fig 3-4, step 404 fig 4, step 504 fig 5].
With respect to dependent claim 6 Bassett/Ramaraju/Randall discloses address calculation circuitry to determine the target address based on a combination of a base address and an offset, wherein the lookup circuitry is configured to determine the imprecise lookup value based on an imprecise combination of the base address and offset [PG/PGZ encoding uses imprecise combination of base + offset – Ramaraju 0020, 0024, 0026-0028, fig 7].
With respect to dependent claim 7 Bassett/Ramaraju/Randall discloses wherein the lookup circuitry is configured to exclude at least one carry operation from determination of the imprecise lookup value [at least the xor logic gates is operable to exclude at least one carry operation – Ramaraju 0026. Stated another way, the limited carry information and speculative row selection disclosed by Ramaraju effectively excludes at least one carry for the imprecise operand lookup].
With respect to dependent claim 8 Bassett/Ramaraju/Randall discloses wherein the lookup circuitry is configured to determine the imprecise lookup value based on discontiguous portions of the base address [Ramaraju 0026, fig 3-4, 7].
With respect to dependent claim 10 Bassett/Ramaraju/Randall discloses wherein the control information comprises address mapping information identifying a physical page of memory corresponding to the given address [Bassett 0023, fig 2].
With respect to dependent claim 12 Bassett/Ramaraju/Randall discloses wherein in at least one mode the lookup circuitry is configured to perform the precise lookup operation for a given target address without performing the imprecise lookup operation at least in response to a prediction that the imprecise lookup operation will not hit in the second control information storage [imprecise lookup is selective/optional - Bassett 0005].
With respect to dependent claim 13 Bassett/Ramaraju/Randall discloses wherein the plurality of control information entries are configured to store tag information, and the imprecise lookup operation comprises identifying a candidate set of one or more candidate control information entries using the imprecise lookup value, and determining whether the candidate set comprises the target control information entry based on a comparison between a tag portion of the target address and the tag information provided by the one or more candidate control information entries [Ramaraju fig 3-5].
With respect to dependent claim 14 Bassett/Ramaraju/Randall discloses wherein the lookup circuitry is configured to identify no more than one control information entry in the second control information storage for a given imprecise lookup value [Ramaraju fig 3-5, paragraph 0035, 0037, 0047-0048].
With respect to dependent claim 16 Bassett/Ramaraju/Randall discloses: A system comprising: the apparatus of claim 1, implemented in at least one packaged chip; at least one system component; and a board, wherein the at least one packaged chip and the at least one system component are assembled on the board [Bassett fig 1, 6].
With respect to dependent claim 17 Bassett/Ramaraju/Randall discloses: A chip-containing product comprising the system of claim 16, wherein the system is assembled on a further board with at least one other product component [Bassett fig 1, 6].
Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable over Bassett/Ramaraju/Randall further in view of Kaniyur (US PGPUB # 20070061549)
With respect to dependent claim 2 Bassett/Ramaraju/Randall does not explicitly disclose all limitations of the instant claim. Nevertheless in the same field of endeavor Kaniyur teaches means for address translation where the method includes initiating a page walk if none of a plurality of entries in a translation lookaside buffer (TLB) in a direct memory access (DMA) remap engine matches a guest physical address of an incoming address translation request (Kaniyur abstract). The combination Bassett/Ramaraju/Randall/Kaniyur discloses allocation circuitry responsive to a determination that the precise lookup operation for a given target address missed in the first control information storage and the imprecise lookup value did not correspond to the given target address, to allocate a control information entry corresponding to the given target address in the first control information storage [base only (speculative) lookup is wrong/misses causing, base + offset (effective address) lookup to be performed – Bassett fig 4-5; allocating a control information entry corresponding to the given target address - Kaniyur 0020, claim 3]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to allocate a control information entry corresponding to a given target address in the invention of Bassett/Ramaraju/Randall as taught by Kaniyur because it would be advantageous for resolving TLB misses when performing address lookups via page walk – Kaniyur 0006.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Bassett/Ramaraju/Randall further in view of Banerjee (US PGPUB # 20060206686)
With respect to dependent claim 9 Bassett/Ramaraju/Randall does not explicitly disclose all limitations of the instant claim. Nevertheless in the same field of endeavor Banerjee teaches a three-tiered TLB hierarchy (Banerjee abstract). The combination Bassett/Ramaraju/Randall/Banerjee discloses wherein the first control information storage is configured to support a superset of entries supported by the second control information storage [A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread – Banerjee abstract ]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use storage that would support a superset of entries relative to another in the invention of Bassett/Ramaraju/Randall as taught by Banerjee because it would be advantageous for improving memory paging performance – Banerjee 0005-0007.
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Bassett/Ramaraju/Randall further in view of Gupta (US Patent # 10963392)
With respect to dependent claim 11 Bassett/Ramaraju/Randall does not explicitly disclose all limitations of the instant claim. Nevertheless in the same field of endeavor Gupta teaches efficiently handling data selected for eviction in a computing system (Gupta abstract). The combination Bassett/Ramaraju/Randall/Gupta discloses allocation circuitry configured to allocate, to the second control information storage, control information entries evicted from the first control information storage [cache controller of the first cache includes an allocator for determining whether to allocate data evicted from the first cache (first control information storage) into the victim cache (second control information storage) – Gupta abstract, col 1 line 60 – col 2 line 8]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use allocation circuitry configured to allocate, to a second control information storage, control information entries evicted from a first control information storage in the invention of Bassett/Ramaraju/Randall as taught by Gupta because it would be advantageous for improving efficiency in handling evicted data – Gupta col 1 lines 55-60.
Claims 15 are rejected under 35 U.S.C. 103 as being unpatentable over Bassett/Ramaraju/Randall further in view of Banerjee (US PGPUB # 20060206686)
With respect to dependent claim 15 Bassett/Ramaraju/Randall does not explicitly disclose all limitations of the instant claim. Nevertheless in the same field of endeavor Banerjee teaches a three-tiered TLB hierarchy (Banerjee abstract). The combination Bassett/Ramaraju/Randall/Banerjee discloses wherein the second control information storage comprises a greater number of control information entries than the first control information structure. [A macro-TLB (second control information storage) caches address translation information for memory pages for all the threads. A micro-TLB (first control information storage) caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread – Banerjee abstract ]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use storage wherein a second control information storage comprises a greater number of control information entries than a first control information structure in the invention of Bassett/Ramaraju/Randall as taught by Banerjee because it would be advantageous for improving memory paging performance – Banerjee 0005-0007.
Response to Arguments
Applicant's arguments have been fully considered but are not persuasive in view of the prior art. All claims pending in the instant application remain rejected. Please note that any rejections/objection not maintained from the previous Office Action have been rectified either by applicant's amendment and/or persuasive argument(s).
Regarding applicant’s arguments on page 8-11, that amended claims are not taught by the cited art [The examiner respectfully submits that amended grounds of rejection necessitated by amendments to the claims have rendered the remarks moot/unpersuasive, particularly in view of the combination of prior art including newly found Randall reference as integrated into the rationale above.]
Remaining arguments are understood to be predicated on the previous arguments being persuasive and thus are unpersuasive at least on dependency merits.
All remarks are understood to have been addressed herein. If any issues remain which may be clarified by the examiner, the applicant is invited to contact the examiner to set up a telephone interview.
When responding to the office action, any new claims and/or limitations should be accompanied by a reference as to where the new claims and/or limitations are supported in the original disclosure.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARWAN AYASH whose telephone number is (571)270-1179. The examiner can normally be reached 9a-730p M-R.
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/Marwan Ayash/ - Examiner - Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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