Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to arguments
This communication is in response to filing of 06/30/2026. Claims 1-19 are pending. Applicant’s arguments with respect to Rejection under 35 USC 101 have been fully considered and are persuasive. Applicant’s arguments with respect to the rejection of claim 7 under 35 USC 112 lacks any substantive amendment that corresponds to in applicant’s remarks filed 06/30/2026 as the alleged amendments to claim 7 are nonexistent. No amendment to claim 7 has been filed, and thus the associated rejection under 35 USC 112 is maintained. Applicant’s arguments with respect to prior art rejections of amended claim(s) have been fully considered but they are not persuasive for the following reasons:
Applicant’s Argument:
“While Rogers discloses that restricted data can be deleted from the TEE, there is no
disclosure or suggestion of the related process data from the shared memory into the restricted memory. For at least these reasons, Rogers fails to remedy the deficiency of Chen as alleged.
In summary, Chen and Rogers when applied individually and/or collectively as alleged in the Office Action, fail to disclose or suggest every feature and/or the combination of features recited in Applicant's claims. Withdrawal of this rejection, therefore, is respectfully requested."
Examiner’s Response:
The examiner respectfully disagrees. In addition to Rogers’ disclosure that restricted data can be deleted from the TEE, Rogers also suggests that related process data from the shared memory is transferred into the restricted memory. Rogers discloses that [0084]“As described herein, to secure the composite TEE 150 including the GPU 104, the VM 116 and the secure processor 146 of the GPU 104 may negotiate a shared key. In such examples, the secure processor 146 may operate as the root of trust for the GPU 104 within the composite TEE 150. Furthermore, direct memory access between the CPU 102 (e.g., the VM 116) and the GPU 104 can be secured using the shared key and a bounce buffer 110A, 110B, or similar unsecure memory region to transmit data.” And that [0098] “Similarly, when transmitting data from the protected region(s) 336 of the GPU(s) 104 to the CPU TEE 170, in various embodiments, the memory accessor 130 encrypts the data to generate encrypted data and copies the encrypted data (e.g., transmits the data across the system bus 320), using the buffer 310, to the unsecure region 318 of the memory 342. In response, the CPU TEE 170 (e.g., the driver(s) 122) may obtain the encrypted data from the buffer 310 and decrypt the encrypted data using the shared key 168 such that the data is in plain text and accessible to one or more components within the CPU TEE 170.”, providing for an embodiment where the unsecure, or shared, memory region is used to transfer data to the TEE, or restricted memory, by way of a shared key negotiated between them.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 7, the phrase "preferably" renders the claim indefinite because it is unclear whether the limitations following the phrase are part of the claimed invention. See MPEP § 2173.05(d).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHEN (US 20200250302 A1), hereafter CHEN, in view of ROGERS (US 20230297696 A1), hereafter ROGERS.
Regarding claim 1, CHEN teaches:
A computer-implemented method for improving data security in a computing device([0006] "This application provides a computer system, a terminal device, a security control method applied to the computer system and the terminal device, and the like, to improve security of the terminal device or another type of computer system.”), the computing device including a computer system with a processor for executing computer instructions and a physical memory accessible to the processor([0048] “According to a fifth aspect, this application further provides a computer system. A hardware layer of the computer system includes a tracer, a processor, and a memory. The computer system can be logically divided into a first domain and a second domain. The processor is configured to: read a computer readable instruction from the memory, and execute the computer readable instruction, to start the tracer and execute a program in the first domain.”), the computer system being configured as an implementation of a computer architecture suitable for switching between a trusted execution environment for executing a trusted computing process and a rich execution environment for executing a client computing process corresponding to the trusted computing process([0004] “The TEE can ensure that sensitive data is stored, processed, and protected in the trusted environment, and provides a secure execution environment for an authorized trusted application (trusted application, TA). A client application (client application, CA) (also referred to as a normal application) runs in the REE.”, [0097] “When the SMC calling module 220 sends the trigger message to the audit module 240, switching from the REE to the TEE is required.”), wherein an access of the rich execution environment on the trusted execution environment is restricted and/or secured([0004] “The CA accesses the TA by calling an application programming interface (application programming interface, API) of a TEE client in the REE, to use a security function provided by the TEE and the TA.”), wherein the rich execution environment and the trusted execution environment respectively are switchable between a user mode in which execution of one or more selected computer instructions for accessing the physical memory is restricted and/or secured, and a kernel mode in which execution of said computer instructions is unrestricted and/or unsecured([0019] “In some implementations, the first domain and the second domain are respectively an insecure world and a secure world (which may also be construed as a REE and a TEE) that are based on TrustZone.”, [0090] “The terminal device 200 includes two domains: a rich execution environment (rich execution environment, REE) and a trusted execution environment (trusted execution environment, TEE). A Linux® operating system and a TEE-side operating system (for example, an open-source OP-TEE operating system) respectively run in the two domains. The Linux® operating system and the TEE OS each are divided into two states: a user mode and a kernel mode.”), wherein the rich execution environment and the trusted execution environment commonly use a shared memory of the physical memory, the shared memory providing a communication channel including related process data for communication between the client computing process and the trusted computing process([0119] “Specifically, when a CA on the REE side performs cross-domain calling, the CA usually stores, in shared memory, a PID of a process of the CA, an identifier and a parameter of a TA that the CA expects to call, and the like. In this way, a module on the TEE side can obtain, from the shared memory, a value of the PID of the process.”), the method comprising: a) by the computing device, providing a restricted memory, wherein the access to the restricted memory is restricted and/or secured with respect to the processor([0162] “It should be noted that an EL is an abbreviation for an exception level, and is a concept in ARM®. In a manner, the EL0 may be construed as a user mode, the EL1 is construed as a kernel mode, the EL2 is a hypervisor, and an EL3 is a secure mode. The EL2 can control access to physical memory from the EL0 and the EL1. In the foregoing embodiment, it means that a page table is configured at the EL2, so that accessing a physical memory address of the register of the CoreSight 270 from the EL0 and the EL1 is restricted.”); b) by the computer system, upon receiving a computer instruction for switching from the user mode to the kernel mode inside the rich execution environment, triggering the computing device ([0014] “The automaton may respond to an external input (for example, an event), to switch from a state to another state.”, [0090] “The Linux® operating system and the TEE OS each are divided into two states: a user mode and a kernel mode.”)
Further regarding claim 1, CHEN teaches the limitations previously demonstrated, but does not appear to explicitly teach the following limitations demonstrated by ROGERS:
to perform the following: α) transferring the related process data ([0089] “In one or more embodiments, the GPU 104 may be required to reset in order to switch the GPU 104 from non-secure to secure mode, or from secure mode to non-secure mode.”, [0150] “For example, the secure processor 146 may cause the GPU 104 to perform a reset. After the GPU 104 is reset, the system 100 may delete, clean, and/or scrub data from GPU memory, such as the memory 334 and/or GPU state data (as described herein). In at least one embodiment, all contents of GPU memory is deleted. In at least one embodiment, the secure processor 146 and/or GPU firmware (e.g., after reset) scrubs and/or deletes the contents of the GPU memory and a GPU copy of the shared cryptographic key(s) 168 to ensure data generated within the composite TEE 150 is not exposed. In at least one embodiment, scrubbing and/or deleting the contents of the GPU memory may include deleting the contents of one or more protected region(s) 336. In at least one embodiment, scrubbing completes before the memory 334 is made visible on the system bus 320.”).
Since CHEN and ROGERS are from the same field of endeavor as both are directed to secure transmission between computing domains, which is within the same field of endeavor as the claimed invention, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to modify and combine the teachings of CHEN and ROGERS by incorporating the teachings of ROGERS into CHEN. The motivation to combine is to improve secure cross-domain transmission and verification thereof. (CHEN [AB]; ROGERS [AB]). This motivation is equally applicable for rejections hereafter.
Regarding claim 2, CHEN-ROGERS teaches:
The method according to claim 1, further comprising: d) by the computer system, upon receiving a computer instruction for switching from the kernel mode of the trusted execution environment to the kernel mode of the rich execution environment, triggering the computing device to perform step α); and e) by the computing device, performing step α)(CHEN [0014] “The automaton may respond to an external input (for example, an event), to switch from a state to another state.”, [0090] “The Linux® operating system and the TEE OS each are divided into two states: a user mode and a kernel mode.”, ROGERS [0089] “In one or more embodiments, the GPU 104 may be required to reset in order to switch the GPU 104 from non-secure to secure mode, or from secure mode to non-secure mode.”, [0150] “For example, the secure processor 146 may cause the GPU 104 to perform a reset. After the GPU 104 is reset, the system 100 may delete, clean, and/or scrub data from GPU memory, such as the memory 334 and/or GPU state data (as described herein). In at least one embodiment, all contents of GPU memory is deleted. In at least one embodiment, the secure processor 146 and/or GPU firmware (e.g., after reset) scrubs and/or deletes the contents of the GPU memory and a GPU copy of the shared cryptographic key(s) 168 to ensure data generated within the composite TEE 150 is not exposed. In at least one embodiment, scrubbing and/or deleting the contents of the GPU memory may include deleting the contents of one or more protected region(s) 336. In at least one embodiment, scrubbing completes before the memory 334 is made visible on the system bus 320.”).
Regarding claim 3, CHEN-ROGERS teaches:
The method according to claim 1, further comprising: f) storing a physical location for localizing the communication channel in the physical memory and clearing the related process data in the shared memory by localizing the communication channel in the physical memory based on the physical location(ROGERS [0055] “For example, the hypervisor 118 may write data through an out of band (OOB) channel to a memory location(s) in a programmable read-only memory (PROM), such as an electrically erasable programmable read-only memory (EEPROM) attached to the GPU 104 (e.g., non-volatile memory).”, [0056] “the hypervisor 118 may again use the communication channel(s) 162 to indicate to the GPU 104 to exit the secure execution mode and/or the confidential compute mode on the next reset (e.g., by writing data in the PROM).”).
Regarding claim 4, CHEN-ROGERS teaches:
The method according to claim 1, further comprising: g) by the computer system, upon receiving a computer instruction for switching from the kernel mode to the user mode inside the rich execution environment, triggering the computing device to perform the following: β) transferring the related process data from the restricted memory into the communication channel of the shared memory by identifying the client computing process in the rich execution environment; and h) by the computing device, performing step β)(CHEN [0004] “A client application (client application, CA) (also referred to as a normal application) runs in the REE. The CA accesses the TA by calling an application programming interface (application programming interface, API) of a TEE client in the REE, to use a security function provided by the TEE and the TA.”, [0119] “Specifically, when a CA on the REE side performs cross-domain calling, the CA usually stores, in shared memory, a PID of a process of the CA, an identifier and a parameter of a TA that the CA expects to call, and the like.”).
Regarding claim 5, CHEN-ROGERS teaches:
The method according to claim 1, further comprising: i) by the computer system, upon receiving a computer instruction for switching from the kernel mode of the rich execution environment to the kernel mode of the trusted execution environment, triggering the computing device to perform the following: β) transferring the related process data from the restricted memory into the communication channel of the shared memory by identifying the client computing process in the rich execution environment; and j) by the computing device, performing step β) (CHEN [0004] “A client application (client application, CA) (also referred to as a normal application) runs in the REE. The CA accesses the TA by calling an application programming interface (application programming interface, API) of a TEE client in the REE, to use a security function provided by the TEE and the TA.”, [0119] “Specifically, when a CA on the REE side performs cross-domain calling, the CA usually stores, in shared memory, a PID of a process of the CA, an identifier and a parameter of a TA that the CA expects to call, and the like.”, [0019] “In some implementations, the first domain and the second domain are respectively an insecure world and a secure world (which may also be construed as a REE and a TEE) that are based on TrustZone” [0075] “Alternatively, the first operating system and the second operating system may be two different states of a same operating system, for example, a user mode and a kernel mode. In other words, the first domain and the second domain are two states of a same operating system.” [0090] “The terminal device 200 includes two domains: a rich execution environment (rich execution environment, REE) and a trusted execution environment (trusted execution environment, TEE).”).
Regarding claim 6, CHEN-ROGERS teaches:
The method according to claim 4, further comprising: k) storing a process identifier for identifying the client computing process in the rich execution environment and identifying the client computing process in the rich execution environment based on the process identifier(CHEN [0119] “Specifically, when a CA on the REE side performs cross-domain calling, the CA usually stores, in shared memory, a PID of a process of the CA, an identifier and a parameter of a TA that the CA expects to call, and the like. In this way, a module on the TEE side can obtain, from the shared memory, a value of the PID of the process. The audit module 240 searches for an automaton instance whose identifier is the value of the PID (S708). If the automaton instance does not exist (S709), the current audit fails. If the automaton instance exists (S709), the audit module 240 determines whether the automaton instance is currently in a state with an attribute “termination” (briefly referred to as a termination state). If yes, the audit succeeds”).
Regarding claim 7, CHEN-ROGERS teaches:
The method according to claim 1, further comprising: l) monitoring an integrity of a computer instruction for triggering the computing device to transfer the related process data into or out of the restricted memory (CHEN [0012] “Data flow: A data flow represents a data read/write procedure of a program, and includes data in the procedure. The data flow may be directly or indirectly represented as a data read/write event sequence of the program. In some embodiments of this application, data included in the read/write event sequence is audited to ensure system security.”, [0018] “A tracer is further deployed in the terminal device, to implement integrity audit on a control flow of the program together with the control flow module and the audit module.”), preferably by calculating a hash of said computer instruction, and transferring the related process data into or out of the restricted memory based on the monitored integrity(CHEN [0027] “The audit module is specifically configured to: obtain the hash value H1; obtain a hash value H2 through calculation based on the random number RX and the text segment included in the second domain; compare H1 with H2; and when H1 is the same as H2 and other to-be-audited information matches the audit rule, determine that the audit succeeds.", [0039] “After the audit method is applied to security control, a next operation is allowed after the audit succeeds.”).
Regarding claim 8, CHEN-ROGERS teaches:
A computing device including a computer system with a processor for executing computer instructions and a physical memory accessible to the processor, the computer system being configured as an implementation of a computer architecture suitable for switching between a trusted execution environment for executing a trusted computing process and a rich execution environment for executing a client computing processcommunication between the client computing process and the trusted computing process, wherein the computing device provides a restricted memory, wherein the access to the restricted memory is restricted and/or secured with respect to the processor, and wherein the computing device executes instructions causing the computing device to perform the method according to claim 1(CHEN [0006] “This application provides a computer system, a terminal device, a security control method applied to the computer system and the terminal device, and the like, to improve security of the terminal device or another type of computer system.”, [0048] “According to a fifth aspect, this application further provides a computer system. A hardware layer of the computer system includes a tracer, a processor, and a memory. The computer system can be logically divided into a first domain and a second domain. The processor is configured to: read a computer readable instruction from the memory, and execute the computer readable instruction, to start the tracer and execute a program in the first domain. The hardware tracer is configured to: when the program is executed, collect to-be-audited information related to the program.”).
Regarding claim 9, CHEN-ROGERS teaches:
The computing device according to claim 8, wherein the computing device executes instruction causing the hardware to perform one, several or all of the following: α) transferring the related process data from the shared memory into the restricted memory and clearing the related process data in the shared memory; and/or β) transferring the related process data from the restricted memory into the communication channel of the shared memory by identifying the client computing process in the rich execution environment; and/or f) storing a physical location for localizing the communication channel in the physical memory and clearing the related process data in the shared memory by localizing the communication channel in the physical memory based on the physical location(CHEN [0048] “According to a fifth aspect, this application further provides a computer system. A hardware layer of the computer system includes a tracer, a processor, and a memory. The computer system can be logically divided into a first domain and a second domain. The processor is configured to: read a computer readable instruction from the memory, and execute the computer readable instruction, to start the tracer and execute a program in the first domain. The hardware tracer is configured to: when the program is executed, collect to-be-audited information related to the program.”).
Regarding claim 10, CHEN-ROGERS teaches:
The computing device according to claim 8, wherein the computing device includes a field-programmable gate array providing the restricted memory(CHEN [0244] “In the hardware implementation, implementations of this application may be implemented by using at least one of electronic units such as an application-specific integrated circuit (application-specific integrated circuit, ASIC), a digital signal processor (digital signal processor, DSP), a programmable logic device (programmable logic device, PLD), a field programmable gate array (field programmable gate array, FPGA),”).
Regarding claim 11, CHEN-ROGERS teaches:
The computing device according to claim 10, wherein the instructions cause the field-programmable gate array to perform one, several or all of the steps α), β), f), k), and/or l) (CHEN [0244] “In the hardware implementation, implementations of this application may be implemented by using at least one of electronic units such as an application-specific integrated circuit (application-specific integrated circuit, ASIC), a digital signal processor (digital signal processor, DSP), a programmable logic device (programmable logic device, PLD), a field programmable gate array (field programmable gate array, FPGA),”).
Regarding claim 12, CHEN-ROGERS teaches:
The computing device according to claim 8, wherein software of the computing device includes instructions that trigger the computing device to perform the step α) and/or β) (CHEN [0037] “In some implementations, trigger instructions are inserted at a plurality of locations in the program, to trigger the tracer to collect control flow information at a specific location.”).
Regarding claim 13, CHEN-ROGERS teaches:
The computing device according to claim 11, wherein the computer system executes the instruction which trigger the field-programmable gate array to perform the step α) and/or β)(CHEN [0037] “In some implementations, trigger instructions are inserted at a plurality of locations in the program, to trigger the tracer to collect control flow information at a specific location.”, [0244] “In the hardware implementation, implementations of this application may be implemented by using at least one of electronic units such as an application-specific integrated circuit (application-specific integrated circuit, ASIC), a digital signal processor (digital signal processor, DSP), a programmable logic device (programmable logic device, PLD), a field programmable gate array (field programmable gate array, FPGA)”).
Regarding claim 14, claim 14 recites substantially similar limitations as claim 1, but for recitation in the form of a computer storage device storing instructions. Accordingly, claim 14 is rejected for similar reasoning and rationale as claim 1. CHEN-ROGERS further teaches:
A computer storage device storing instructions which, when the program is executed by a computing device including a computer system with a processor for executing computer instructions and a physical memory accessible to the processor, the computer system being configured as an implementation of a computer architecture suitable for switching between a trusted execution environment for executing a trusted computing process and a rich execution environment for executing a client computing process corresponding to the trusted computing process, wherein an access of the rich execution environment on the trusted execution environment is restricted and/or secured, wherein the rich execution environment and the trusted execution environment respectively are switchable between a user mode in which execution of one or more selected computer instructions for accessing the physical memory is restricted and/or secured, and a kernel mode in which execution of said computer instructions is unrestricted and/or unsecured, wherein the rich execution environment and the trusted execution environment commonly use a shared memory of the physical memory, the shared memory providing a communication channel including related process data for communication between the client computing process and the trusted computing process, wherein the computing device provides a restricted memory, wherein the access to the restricted memory is restricted and/or secured with respect to the processor, cause the computing device to carry out the method according to claim 1(CHEN [claim 1] “a memory storing computer readable instructions; and a processor in communication with the tracer and the memory, the processor is configured to: execute the computer readable instructions;”, [0047] “According to a fourth aspect, this application further provides a computer program product. The computer program product includes a computer readable instruction. When the computer readable instruction is executed by one or more processors, the computer readable instruction is used to implement any one of the foregoing methods.”).
Regarding claim 15, claim 15 recites substantially similar limitations as claim 1, but for recitation in the form of a non-transitory computer-readable medium. Accordingly, claim 15 is rejected for similar reasoning and rationale as claim 1. CHEN-ROGERS further teaches:
A non-transitory computer-readable storage medium having stored thereon the computer program according to claim 14(ROGERS [0210] “The computer-storage media may include both volatile and nonvolatile media and/or removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules, and/or other data types. For example, the memory 1704 may store computer-readable instructions (e.g., that represent a program(s) and/or a program element(s), such as an operating system. Computer-storage media may include, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which may be used to store the desired information and which may be accessed by computing device 1700. As used herein, computer storage media does not comprise signals per se.”).
Regarding claim 16, CHEN-ROGERS teaches:
The method according to claim 5, further comprising: k) storing a process identifier for identifying the client computing process in the rich execution environment (CHEN [0119] “Specifically, when a CA on the REE side performs cross-domain calling, the CA usually stores, in shared memory, a PID of a process of the CA, an identifier and a parameter of a TA that the CA expects to call, and the like.”)and identifying the client computing process in the rich execution environment based on the process identifier(CHEN [0078] “The information (referred to as to-be-audited information below) may include one or more types of the following information: control flow information that is related to code running and that is used for control flow audit…a process ID (process identification, PID) that is used to identify the to-be-protected program in parallel audit).
Regarding claim 17, CHEN-ROGERS teaches:
The computing device according to claim 9, wherein the computing device includes a field-programmable gate array providing the restricted memory (CHEN [0244] “In the hardware implementation, implementations of this application may be implemented by using at least one of… a field programmable gate array (field programmable gate array, FPGA)”).
Regarding claim 18, CHEN-ROGERS teaches:
The computing device according to claim 10, wherein the instruction cause the field-programmable gate array to perform one, several or all of the steps α), β), f), k), and/or l) (CHEN [0244] “In the hardware implementation, implementations of this application may be implemented by using at least one of… a field programmable gate array (field programmable gate array, FPGA)”).
Regarding claim 19, CHEN-ROGERS teaches:
The computing device according to claim 12, wherein the instructions cause the computer system is adapted to trigger the field-programmable gate array to perform the step α) and/or β) (CHEN [0244] “In the hardware implementation, implementations of this application may be implemented by using at least one of… a field programmable gate array (field programmable gate array, FPGA)”, [0037] “In some implementations, trigger instructions are inserted at a plurality of locations in the program, to trigger the tracer to collect control flow information at a specific location.”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/K.J.G./Examiner, Art Unit 2408
/LINGLAN EDWARDS/Supervisory Patent Examiner, Art Unit 2408
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