DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 7 and 16 were canceled and claims 21-22 were added. Claims 1-6, 8-15 and 17-22 are pending.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8, 12-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Swaminathan 20180226051 in view of Gupta 20240289202.
Regarding claim 1, Swaminathan teaches a method and computing system [Fig 1 and 5], comprising:
a system board comprising at least one component and a processor [Host 180, CPU 182];
a baseboard management controller (BMC) communicatively connected to the processor [BMC 102, 564, par. 4 and 23] ; and
a universal asynchronous receiver-transmitter (UART) interface communicably connecting the processor to the BMC, [par. 33, UART communicating at Serial Port s 115 to 172]
wherein the BMC is configured to, prior to a PCle bus of the computing system being trained [par. 36, steps described in par. 32-37 are done prior to initialization of PCI/PCIe 176, during POST]
initialize at least one UART device of the UART interface; [ par. 1, 7, 20, 22, 32-33, in pre-boot state, UART connected the serial ports during pre-boot initialization state]
transmit a message to the processor via the UART interface [par. 33-34, BMC 102 runs a monitor process, i.e. request status. See also par. 37, POST, par. 25, service 138 of BMC may send/receive IPMI messages]
receive a communication code from the processor using the UART; and [par. 25, 33-34. and 37, 57 BMC obtains data from the CPU 182 on serial port 115, data includes status indicators, error /POST codes, POST codes]
execute a functionality task associated with the data communication code [ par. 34-37, 40-41 BMC provides obtained information to the GPU 152 to for display, including debug or error information, management controller performs error analysis and action]
Though Swaminathan does not specify the message is status request and the communication code is in response to the status request. However, such operation is inherent in error communication messaging in BMC.
In the alternative, Gupta teaches a system [Fig. 3] having BMC [322/326] that communicates with a host via UART and perform pre-boot error reporting [par. 2, 18-19] wherein error reporting is based on a request [Fig. 4, 9A, par. 25, error messages can be transmitted at the request by the BMC via a UART] and
execute functionality task associated with the data communication code [ par. 21, perform debug actions or recoverable action]
It would have been obvious to one having ordinary skill in the art to realize that such operation is part of the communication messaging in BMC for perform reliability, availability, and serviceability (RAS) management [Gupta, par. 21]
Claim 2 . The combination teaches the method of claim 1, Swaminathan further teaches wherein executing the functionality task comprises generating and transmitting to at least one computing component a component instruction instructing the at least one computing component to perform an action associated with the functionality task [par. 34-38, 40-41, receive and transmit status indicator and display the information/debugging ]
Claim 3. The combination teaches the method of claim 2, Swaminathan further teaches wherein the functionality task comprises displaying video images, the at least one computing component comprises a video controller and the component instruction instructs the video controller to display the video images [Fig. 3, par. 34-37, 40-41, 54-56step 306-312 and 322-330, receive and transmit the data at the serial port for playing the video ]
Claim 4. The method of claim 3, Swaminathan further teaches wherein the video images comprise an event message and/or an active health system message [ par. 40-41, debug data or error information, par. 73, health-related aspects associated with the computer system 502]
Claim 5. The method of claim 2, Gupta and Swaminathan teach wherein the functionality task comprises error logging, the at least one computing component comprises a database storing an error log, and the component instruction instructs the database to log an error associated with the received communication code [Gupta, Fig. 3, 314, par. 18-19. S3M 316 can perform error detection, error collection, and error reporting to platform CPLD 322. See also Swaminathan par. 3, 14; system event logging, data written from BMC written to memory 114].
Claim 6. The method of claim 1, Swaminathan teaches wherein the initializing, the receiving, and the executing are performed during a system boot operation prior to the PCIe bus of the computing system being trained [par. 33, pre-boot initialization, does not have access to the host PCI/PCIe interface 176]
Claim 8. The method of claim 1, Gupta teaches wherein the processor sends the communication code to the BMC via the UART in response to receiving the status request from the BMC via the UART [Gupta, Fig. 4, 9A, 11 par. 25, error messages can be transmitted at the request by the BMC via a UART. Par. 39 depicts a system 1100 can detect and report errors. S See also Swaminathan; par. 25 IMPI messaging]
Claim 12. The method of claim 1, Swaminathan further comprising performing a handoff operation in response to a PCIe bus being trained [par. 36, after host computer 180 has initiated the host PCI/PCIe interface 176, GPU 183 can start writing image data to the physical frame buffer 122 of the BMC 102 through the host PCI/PCIe interface 176, Fig. 3, step 344-346, switch ownership]
Claim 13 is an apparatus claims having the same limitations as in claim 1 and rejected accordingly.
Claims 14-15 repeat the same limitation as in claims 2-3 and are rejected accordingly.
Claim 17 repeats the same limitation as in claim 12 and is rejected accordingly.
Claim 18 recites a non-transitory CRM and repeats the limitation of claim 1 wherein the auxiliary communication interface is the UART.
Claim 19 repeats the limitation of claim 2 and therefore rejected accordingly.
Claim 20 repeats the limitation of claim 12 and is rejected accordingly.
Claims 19-11 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Swaminathan in view of Gupta and further in view of Hong 20230195568.
Claim 9. The method of claim 1, Gupta teaches wherein information corresponding to the functionality task is stored in a dataset in association with the communication code, and wherein the method further comprises querying the dataset based on the communication code to determine the functionality task associated with the communication code [Gupta, par. 16-21, 30, 41 reporting of error and failure, error codes, and retrieval of error logs, stored in a memory space that is accessible, apply an error action model based on collected error code. Par. 32, CPLD circuitry can decode the error code information. Par. 65-72 error log and manageability port, description of error code].
In the alternative, Hong teaches error processing in computer system [par. 2-5] having BMC [139, Fig. 4- 6] for managing errors in the computer system and including memory for storing error evens/error codes and dataset to determine functional task [par. 34, 50, 56, 73-84, error data 111 and handling policy, see especially operation described in Fig. 6 ]. It would have been obvious to one having ordinary skill in the art before the effective filing date to include the teaching of Hong to minimize downtime of the server computer and/or performance impact in providing services of the server computer [Hong, par. 21]
Claim 10. (Original) The method of claim 9, Gupta teaches wherein the dataset is a remote database [Gupta, par. 26, 44-45, 48, Fig. 3 and 11, support remote diagnostics and repair. See also Hong, Fig. 7 and par. 128]
Claim 11. The method of claim 9, Gupta teaches wherein the dataset is a local data store [Gupta, 21, log the error information in a System Event Log (SEL) and apply an error action model based on collected error code. par. 32, circuitry can decode the error code information from a processor, Fig. 1180, code/data 186. See also Hong, Fig. 4-5].
Claims 21 and 22, depend on claims 1 and 13 and further recites wherein executing the functionality task comprises searching, by the BMC but does not explicitly mention a lookup table for the associated communication code. Hong teaches a looking up a second data about the error and handling policy [Fig. 4-6, par. 21-29, 98-99, historic PPR data contains results and/or statuses of past repairs; hardware error, setting and/or configuration parameters of the memory module that has the hardware error, the identification/serial number] . It would have been obvious to one having ordinary skill in the art before the effective filing date to include the teaching of Hong to optimize use of repair resources and prioritize error handling strategies and reduce costs [Hong, par. 26 and 26].
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KIM HUYNH/Primary Patent Examiner,
Art Unit 2176
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